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Issue 24067002: MIPS/ARM: Fix benchmarks failures on simulator. Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Fix ARM port Created 7 years, 3 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
11 // with the distribution. 11 // with the distribution.
12 // * Neither the name of Google Inc. nor the names of its 12 // * Neither the name of Google Inc. nor the names of its
13 // contributors may be used to endorse or promote products derived 13 // contributors may be used to endorse or promote products derived
14 // from this software without specific prior written permission. 14 // from this software without specific prior written permission.
15 // 15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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24 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 27
28 #include <stdlib.h> 28 #include <stdlib.h>
29 #include <fpu_control.h>
29 #include <cmath> 30 #include <cmath>
30 #include <cstdarg> 31 #include <cstdarg>
31 #include "v8.h" 32 #include "v8.h"
32 33
33 #if V8_TARGET_ARCH_ARM 34 #if V8_TARGET_ARCH_ARM
34 35
35 #include "disasm.h" 36 #include "disasm.h"
36 #include "assembler.h" 37 #include "assembler.h"
37 #include "codegen.h" 38 #include "codegen.h"
38 #include "arm/constants-arm.h" 39 #include "arm/constants-arm.h"
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729 730
730 void Simulator::Initialize(Isolate* isolate) { 731 void Simulator::Initialize(Isolate* isolate) {
731 if (isolate->simulator_initialized()) return; 732 if (isolate->simulator_initialized()) return;
732 isolate->set_simulator_initialized(true); 733 isolate->set_simulator_initialized(true);
733 ::v8::internal::ExternalReference::set_redirector(isolate, 734 ::v8::internal::ExternalReference::set_redirector(isolate,
734 &RedirectExternalReference); 735 &RedirectExternalReference);
735 } 736 }
736 737
737 738
738 Simulator::Simulator(Isolate* isolate) : isolate_(isolate) { 739 Simulator::Simulator(Isolate* isolate) : isolate_(isolate) {
740 set_host_fp_precision();
741
739 i_cache_ = isolate_->simulator_i_cache(); 742 i_cache_ = isolate_->simulator_i_cache();
740 if (i_cache_ == NULL) { 743 if (i_cache_ == NULL) {
741 i_cache_ = new v8::internal::HashMap(&ICacheMatch); 744 i_cache_ = new v8::internal::HashMap(&ICacheMatch);
742 isolate_->set_simulator_i_cache(i_cache_); 745 isolate_->set_simulator_i_cache(i_cache_);
743 } 746 }
744 Initialize(isolate); 747 Initialize(isolate);
745 // Set up simulator support first. Some of this information is needed to 748 // Set up simulator support first. Some of this information is needed to
746 // setup the architecture state. 749 // setup the architecture state.
747 size_t stack_size = 1 * 1024*1024; // allocate 1MB for stack 750 size_t stack_size = 1 * 1024*1024; // allocate 1MB for stack
748 stack_ = reinterpret_cast<char*>(malloc(stack_size)); 751 stack_ = reinterpret_cast<char*>(malloc(stack_size));
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3847 3850
3848 3851
3849 uintptr_t Simulator::PopAddress() { 3852 uintptr_t Simulator::PopAddress() {
3850 int current_sp = get_register(sp); 3853 int current_sp = get_register(sp);
3851 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp); 3854 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp);
3852 uintptr_t address = *stack_slot; 3855 uintptr_t address = *stack_slot;
3853 set_register(sp, current_sp + sizeof(uintptr_t)); 3856 set_register(sp, current_sp + sizeof(uintptr_t));
3854 return address; 3857 return address;
3855 } 3858 }
3856 3859
3860
3861 void Simulator::set_host_fp_precision() {
3862 #if !V8_HOST_ARCH_ARM
3863 // Set Intel x87 FPU mode to 64-bit double.
3864 // The default FPU mode is extended (80-bit),
3865 // which can lead to unexpected precision failures.
3866 fpu_control_t cw;
3867 _FPU_GETCW(cw);
3868 cw &= ~_FPU_EXTENDED;
3869 cw |= _FPU_DOUBLE;
3870 _FPU_SETCW(cw);
3871 #endif
3872 }
3873
3874
3857 } } // namespace v8::internal 3875 } } // namespace v8::internal
3858 3876
3859 #endif // USE_SIMULATOR 3877 #endif // USE_SIMULATOR
3860 3878
3861 #endif // V8_TARGET_ARCH_ARM 3879 #endif // V8_TARGET_ARCH_ARM
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