Switchable call scheduling.

runtime/vm/instructions_arm64.cc

Index: runtime/vm/instructions_arm64.cc
diff --git a/runtime/vm/instructions_arm64.cc b/runtime/vm/instructions_arm64.cc
index 3bd5c3fb8d32f51e9c093dc0083a41b3943e9ce5..674e68a3f19e7b3a5a77eaefea368ed58c559822 100644
--- a/runtime/vm/instructions_arm64.cc
+++ b/runtime/vm/instructions_arm64.cc
@@ -342,15 +342,15 @@ SwitchableCallPattern::SwitchableCallPattern(uword pc, const Code& code)
   ASSERT(*(reinterpret_cast<uint32_t*>(pc) - 1) == 0xd63f0200);
 
   Register reg;
-  uword stub_load_end =
-      InstructionPattern::DecodeLoadWordFromPool(pc - 2 * Instr::kInstrSize,
+  uword data_load_end =
+      InstructionPattern::DecodeLoadWordFromPool(pc - Instr::kInstrSize,
                                                  &reg,
-                                                 &target_pool_index_);
-  ASSERT(reg == CODE_REG);
-  InstructionPattern::DecodeLoadWordFromPool(stub_load_end,
-                                             &reg,
-                                             &data_pool_index_);
+                                                 &data_pool_index_);
   ASSERT(reg == R5);
+  InstructionPattern::DecodeLoadWordFromPool(data_load_end - Instr::kInstrSize,
+                                             &reg,
+                                             &target_pool_index_);
+  ASSERT(reg == CODE_REG);
 }