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Side by Side Diff: src/base/atomicops_internals_x86_gcc.h

Issue 2395553002: Reland "Turn libbase into a component" (Closed)
Patch Set: Created 4 years, 2 months ago
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1 // Copyright 2010 the V8 project authors. All rights reserved. 1 // Copyright 2010 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 // This file is an internal atomic implementation, use atomicops.h instead. 5 // This file is an internal atomic implementation, use atomicops.h instead.
6 6
7 #ifndef V8_BASE_ATOMICOPS_INTERNALS_X86_GCC_H_ 7 #ifndef V8_BASE_ATOMICOPS_INTERNALS_X86_GCC_H_
8 #define V8_BASE_ATOMICOPS_INTERNALS_X86_GCC_H_ 8 #define V8_BASE_ATOMICOPS_INTERNALS_X86_GCC_H_
9 9
10 #include "src/base/base-export.h"
11
10 namespace v8 { 12 namespace v8 {
11 namespace base { 13 namespace base {
12 14
13 // This struct is not part of the public API of this module; clients may not 15 // This struct is not part of the public API of this module; clients may not
14 // use it. 16 // use it.
15 // Features of this x86. Values may not be correct before main() is run, 17 // Features of this x86. Values may not be correct before main() is run,
16 // but are set conservatively. 18 // but are set conservatively.
17 struct AtomicOps_x86CPUFeatureStruct { 19 struct AtomicOps_x86CPUFeatureStruct {
18 bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence 20 bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
19 // after acquire compare-and-swap. 21 // after acquire compare-and-swap.
20 #if !defined(__SSE2__) 22 #if !defined(__SSE2__)
21 bool has_sse2; // Processor has SSE2. 23 bool has_sse2; // Processor has SSE2.
22 #endif 24 #endif
23 }; 25 };
24 extern struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures; 26 V8_BASE_EXPORT extern struct AtomicOps_x86CPUFeatureStruct
27 AtomicOps_Internalx86CPUFeatures;
25 28
26 #define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory") 29 #define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
27 30
28 // 32-bit low-level operations on any platform. 31 // 32-bit low-level operations on any platform.
29 32
30 inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr, 33 inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
31 Atomic32 old_value, 34 Atomic32 old_value,
32 Atomic32 new_value) { 35 Atomic32 new_value) {
33 Atomic32 prev; 36 Atomic32 prev;
34 __asm__ __volatile__("lock; cmpxchgl %1,%2" 37 __asm__ __volatile__("lock; cmpxchgl %1,%2"
(...skipping 231 matching lines...) Expand 10 before | Expand all | Expand 10 after
266 } 269 }
267 270
268 #endif // defined(__x86_64__) 271 #endif // defined(__x86_64__)
269 272
270 } // namespace base 273 } // namespace base
271 } // namespace v8 274 } // namespace v8
272 275
273 #undef ATOMICOPS_COMPILER_BARRIER 276 #undef ATOMICOPS_COMPILER_BARRIER
274 277
275 #endif // V8_BASE_ATOMICOPS_INTERNALS_X86_GCC_H_ 278 #endif // V8_BASE_ATOMICOPS_INTERNALS_X86_GCC_H_
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