Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(532)

Issues Search
    My Issues | Starred     Open | Closed | All

Unified Diff: tests_lit/llvm2ice_tests/64bit.pnacl.ll

Issue 2384433002: [Subzero][MIPS] Implement conditional branches with 64-bit integer compares (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Removed changes of issue 2376233004 which were added to this patch by mistake Created 4 years, 3 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View side-by-side diff with in-line comments
Download patch
« no previous file with comments | « src/IceTargetLoweringMIPS32.cpp ('k') | no next file » | no next file with comments »
Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
Index: tests_lit/llvm2ice_tests/64bit.pnacl.ll
diff --git a/tests_lit/llvm2ice_tests/64bit.pnacl.ll b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
index 69076fd17f465e1988007e70aafa3e703925f342..aac2c0774592659045769eba49aaa098dde60066 100644
--- a/tests_lit/llvm2ice_tests/64bit.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
@@ -1300,6 +1300,30 @@ if.end3: ; preds = %if.then2, %if.end
; ARM32: bl {{.*}} <func>
; ARM32: bx
+; MIPS32-LABEL: icmpEq64
+; MIPS32: xor [[T1:.*]],{{.*}},{{.*}}
+; MIPS32: xor [[T2:.*]],{{.*}},{{.*}}
+; MIPS32: or [[T3:.*]],[[T1]],[[T2]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sltiu [[T4:.*]],[[T3]],1
+; MIPS32-OM1: sw [[T4]],[[MEM:.*]]
Jim Stichnoth 2016/09/29 13:52:20 I am very impressed by the level of detail in thes
+; MIPS32-OM1: lb [[T5:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T5]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: xor [[T1:.*]],{{.*}},{{.*}}
+; MIPS32: xor [[T2:.*]],{{.*}},{{.*}}
+; MIPS32: or [[T3:.*]],[[T1]],[[T2]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sltiu [[T4:.*]],[[T3]],1
+; MIPS32-OM1: sw [[T4]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T5:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T5]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+
declare void @func()
define internal void @icmpNe64(i64 %a, i64 %b, i64 %c, i64 %d) {
@@ -1370,6 +1394,30 @@ if.end3: ; preds = %if.end, %if.then2
; ARM32-O2: beq
; ARM32: bl
+; MIPS32-LABEL: icmpNe64
+; MIPS32: xor [[T1:.*]],{{.*}},{{.*}}
+; MIPS32: xor [[T2:.*]],{{.*}},{{.*}}
+; MIPS32: or [[T3:.*]],[[T1]],[[T2]]
+; MIPS32-O2: beqz [[T3]],{{.*}}
+; MIPS32-OM1: sltu [[T4:.*]],zero,[[T3]]
+; MIPS32-OM1: sw [[T4]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T5:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T5]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: xor [[T1:.*]],{{.*}},{{.*}}
+; MIPS32: xor [[T2:.*]],{{.*}},{{.*}}
+; MIPS32: or [[T3:.*]],[[T1]],[[T2]]
+; MIPS32-O2: beqz [[T3]],{{.*}}
+; MIPS32-OM1: sltu [[T4:.*]],zero,[[T3]]
+; MIPS32-OM1: sw [[T4]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T5:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T5]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+
define internal void @icmpGt64(i64 %a, i64 %b, i64 %c, i64 %d) {
entry:
%cmp = icmp ugt i64 %a, %b
@@ -1424,6 +1472,38 @@ if.end3: ; preds = %if.then2, %if.end
; ARM32-O2: bge
; ARM32: bl
+; MIPS32-LABEL: icmpGt64
+; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32-O2: sltu [[T2:.*]],[[B_HI]],[[A_HI]]
+; MIPS32-O2: xori [[T3:.*]],[[T2]],0x1
+; MIPS32-O2: sltu [[T4:.*]],{{.*}},{{.*}}
+; MIPS32-O2: xori [[T5:.*]],[[T4]],0x1
+; MIPS32-OM1: sltu [[T3:.*]],[[B_HI]],[[A_HI]]
+; MIPS32-OM1: sltu [[T5:.*]],{{.*}},{{.*}}
+; MIPS32: movz [[T3]],[[T5]],[[T1]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T6]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32-O2: slt [[T2:.*]],[[B_HI]],[[A_HI]]
+; MIPS32-O2: xori [[T3:.*]],[[T2]],0x1
+; MIPS32-O2: sltu [[T4:.*]],{{.*}},{{.*}}
+; MIPS32-O2: xori [[T5:.*]],[[T4]],0x1
+; MIPS32-OM1: slt [[T3:.*]],[[B_HI]],[[A_HI]]
+; MIPS32-OM1: sltu [[T5:.*]],{{.*}},{{.*}}
+; MIPS32: movz [[T3]],[[T5]],[[T1]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T6]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+
define internal void @icmpGe64(i64 %a, i64 %b, i64 %c, i64 %d) {
entry:
%cmp = icmp uge i64 %a, %b
@@ -1478,6 +1558,38 @@ if.end3: ; preds = %if.end, %if.then2
; ARM32-O2: blt
; ARM32: bl
+; MIPS32-LABEL: icmpGe64
+; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32-OM1: sltu [[T2:.*]],[[A_HI]],[[B_HI]]
+; MIPS32-OM1: xori [[T3:.*]],[[T2]],0x1
+; MIPS32-OM1: sltu [[T4:.*]],{{.*}},{{.*}}
+; MIPS32-OM1: xori [[T5:.*]],[[T4]],0x1
+; MIPS32-O2: sltu [[T3:.*]],[[A_HI]],[[B_HI]]
+; MIPS32-O2: sltu [[T5:.*]],{{.*}},{{.*}}
+; MIPS32: movz [[T3]],[[T5]],[[T1]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T6]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32-OM1: slt [[T2:.*]],[[A_HI]],[[B_HI]]
+; MIPS32-OM1: xori [[T3:.*]],[[T2]],0x1
+; MIPS32-OM1: sltu [[T4:.*]],{{.*}},{{.*}}
+; MIPS32-OM1: xori [[T5:.*]],[[T4]],0x1
+; MIPS32-O2: slt [[T3:.*]],[[A_HI]],[[B_HI]]
+; MIPS32-O2: sltu [[T5:.*]],{{.*}},{{.*}}
+; MIPS32: movz [[T3]],[[T5]],[[T1]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T6]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+
define internal void @icmpLt64(i64 %a, i64 %b, i64 %c, i64 %d) {
entry:
%cmp = icmp ult i64 %a, %b
@@ -1532,6 +1644,38 @@ if.end3: ; preds = %if.then2, %if.end
; ARM32-O2: bge
; ARM32: bl
+; MIPS32-LABEL: icmpLt64
+; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32-O2: sltu [[T2:.*]],[[A_HI]],[[B_HI]]
+; MIPS32-O2: xori [[T3:.*]],[[T2]],0x1
+; MIPS32-O2: sltu [[T4:.*]],{{.*}},{{.*}}
+; MIPS32-O2: xori [[T5:.*]],[[T4]],0x1
+; MIPS32-OM1: sltu [[T3:.*]],[[A_HI]],[[B_HI]]
+; MIPS32-OM1: sltu [[T5:.*]],{{.*}},{{.*}}
+; MIPS32: movz [[T3]],[[T5]],[[T1]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T6]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32-O2: slt [[T2:.*]],[[A_HI]],[[B_HI]]
+; MIPS32-O2: xori [[T3:.*]],[[T2]],0x1
+; MIPS32-O2: sltu [[T4:.*]],{{.*}},{{.*}}
+; MIPS32-O2: xori [[T5:.*]],[[T4]],0x1
+; MIPS32-OM1: slt [[T3:.*]],[[A_HI]],[[B_HI]]
+; MIPS32-OM1: sltu [[T5:.*]],{{.*}},{{.*}}
+; MIPS32: movz [[T3]],[[T5]],[[T1]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T6]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+
define internal void @icmpLe64(i64 %a, i64 %b, i64 %c, i64 %d) {
entry:
%cmp = icmp ule i64 %a, %b
@@ -1586,6 +1730,38 @@ if.end3: ; preds = %if.end, %if.then2
; ARM32-O2: blt
; ARM32: bl
+; MIPS32-LABEL: icmpLe64
+; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32-OM1: sltu [[T2:.*]],[[B_HI]],[[A_HI]]
+; MIPS32-OM1: xori [[T3:.*]],[[T2]],0x1
+; MIPS32-OM1: sltu [[T4:.*]],{{.*}},{{.*}}
+; MIPS32-OM1: xori [[T5:.*]],[[T4]],0x1
+; MIPS32-O2: sltu [[T3:.*]],[[B_HI]],[[A_HI]]
+; MIPS32-O2: sltu [[T5:.*]],{{.*}},{{.*}}
+; MIPS32: movz [[T3]],[[T5]],[[T1]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T6]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32-OM1: slt [[T2:.*]],[[B_HI]],[[A_HI]]
+; MIPS32-OM1: xori [[T3:.*]],[[T2]],0x1
+; MIPS32-OM1: sltu [[T4:.*]],{{.*}},{{.*}}
+; MIPS32-OM1: xori [[T5:.*]],[[T4]],0x1
+; MIPS32-O2: slt [[T3:.*]],[[B_HI]],[[A_HI]]
+; MIPS32-O2: sltu [[T5:.*]],{{.*}},{{.*}}
+; MIPS32: movz [[T3]],[[T5]],[[T1]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T6]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+
define internal i32 @icmpEq64Bool(i64 %a, i64 %b) {
entry:
%cmp = icmp eq i64 %a, %b
« no previous file with comments | « src/IceTargetLoweringMIPS32.cpp ('k') | no next file » | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698