[Subzero][MIPS] Implement conditional branches with 64-bit integer compares

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
@@ skipping 1282 matching lines @@
 ; ARM32-OM1: tst
 ; ARM32: bne
 ; ARM32: bl {{.*}} <func>
 ; ARM32: cmp
 ; ARM32: cmpeq
 ; ARM32-OM1: tst
 ; ARM32: bne
 ; ARM32: bl {{.*}} <func>
 ; ARM32: bx
 
+; MIPS32-LABEL: icmpEq64
+; MIPS32: xor [[T1:.*]],{{.*}},{{.*}}
+; MIPS32: xor [[T2:.*]],{{.*}},{{.*}}
+; MIPS32: or [[T3:.*]],[[T1]],[[T2]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sltiu [[T4:.*]],[[T3]],1
+; MIPS32-OM1: sw [[T4]],[[MEM:.*]]

[Jim Stichnoth, 2016/09/29 13:52:20]

I am very impressed by the level of detail in these tests.  I would never have
the patience to write these. :)

One suggestion for the future.  Especially for Om1 tests, I would focus on the
"real" instructions like xor/bnez/sltiu that the register allocator will not
affect.  In contrast, loading a register from the stack and storing a register
onto the stack are instructions that might go away in the future if we made some
tweak to improve the Om1 register allocator (unlikely as that might be).  I
think this sw/lb sequence is not there in O2 because of the register allocator.

In other words, it may be more future-proof to avoid specifically testing the
output of a _mov() or a legalizeToReg() operation from the lowering sequence.

+; MIPS32-OM1: lb [[T5:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T5]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: xor [[T1:.*]],{{.*}},{{.*}}
+; MIPS32: xor [[T2:.*]],{{.*}},{{.*}}
+; MIPS32: or [[T3:.*]],[[T1]],[[T2]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sltiu [[T4:.*]],[[T3]],1
+; MIPS32-OM1: sw [[T4]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T5:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T5]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+
 declare void @func()
 
 define internal void @icmpNe64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp ne i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
   br label %if.end
@@ skipping 50 matching lines @@
 ; ARM32-OM1: bne
 ; ARM32-O2: beq
 ; ARM32: bl {{.*}} <func>
 ; ARM32: cmp
 ; ARM32: cmpeq
 ; ARM32-OM1: tst
 ; ARM32-OM1: bne
 ; ARM32-O2: beq
 ; ARM32: bl
 
+; MIPS32-LABEL: icmpNe64
+; MIPS32: xor [[T1:.*]],{{.*}},{{.*}}
+; MIPS32: xor [[T2:.*]],{{.*}},{{.*}}
+; MIPS32: or [[T3:.*]],[[T1]],[[T2]]
+; MIPS32-O2: beqz [[T3]],{{.*}}
+; MIPS32-OM1: sltu [[T4:.*]],zero,[[T3]]
+; MIPS32-OM1: sw [[T4]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T5:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T5]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: xor [[T1:.*]],{{.*}},{{.*}}
+; MIPS32: xor [[T2:.*]],{{.*}},{{.*}}
+; MIPS32: or [[T3:.*]],[[T1]],[[T2]]
+; MIPS32-O2: beqz [[T3]],{{.*}}
+; MIPS32-OM1: sltu [[T4:.*]],zero,[[T3]]
+; MIPS32-OM1: sw [[T4]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T5:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T5]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+
 define internal void @icmpGt64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp ugt i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
@@ skipping 34 matching lines @@
 ; ARM32-OM1: bne
 ; ARM32-O2: bls
 ; ARM32: bl
 ; ARM32: cmp
 ; ARM32: sbcs
 ; ARM32-OM1: tst
 ; ARM32-OM1: bne
 ; ARM32-O2: bge
 ; ARM32: bl
 
+; MIPS32-LABEL: icmpGt64
+; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32-O2: sltu [[T2:.*]],[[B_HI]],[[A_HI]]
+; MIPS32-O2: xori [[T3:.*]],[[T2]],0x1
+; MIPS32-O2: sltu [[T4:.*]],{{.*}},{{.*}}
+; MIPS32-O2: xori [[T5:.*]],[[T4]],0x1
+; MIPS32-OM1: sltu [[T3:.*]],[[B_HI]],[[A_HI]]
+; MIPS32-OM1: sltu [[T5:.*]],{{.*}},{{.*}}
+; MIPS32: movz [[T3]],[[T5]],[[T1]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T6]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32-O2: slt [[T2:.*]],[[B_HI]],[[A_HI]]
+; MIPS32-O2: xori [[T3:.*]],[[T2]],0x1
+; MIPS32-O2: sltu [[T4:.*]],{{.*}},{{.*}}
+; MIPS32-O2: xori [[T5:.*]],[[T4]],0x1
+; MIPS32-OM1: slt [[T3:.*]],[[B_HI]],[[A_HI]]
+; MIPS32-OM1: sltu [[T5:.*]],{{.*}},{{.*}}
+; MIPS32: movz [[T3]],[[T5]],[[T1]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T6]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+
 define internal void @icmpGe64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp uge i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
@@ skipping 34 matching lines @@
 ; ARM32-OM1: bne
 ; ARM32-O2: bcc
 ; ARM32: bl
 ; ARM32: cmp
 ; ARM32: sbcs
 ; ARM32-OM1: tst
 ; ARM32-OM1: bne
 ; ARM32-O2: blt
 ; ARM32: bl
 
+; MIPS32-LABEL: icmpGe64
+; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32-OM1: sltu [[T2:.*]],[[A_HI]],[[B_HI]]
+; MIPS32-OM1: xori [[T3:.*]],[[T2]],0x1
+; MIPS32-OM1: sltu [[T4:.*]],{{.*}},{{.*}}
+; MIPS32-OM1: xori [[T5:.*]],[[T4]],0x1
+; MIPS32-O2: sltu [[T3:.*]],[[A_HI]],[[B_HI]]
+; MIPS32-O2: sltu [[T5:.*]],{{.*}},{{.*}}
+; MIPS32: movz [[T3]],[[T5]],[[T1]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T6]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32-OM1: slt [[T2:.*]],[[A_HI]],[[B_HI]]
+; MIPS32-OM1: xori [[T3:.*]],[[T2]],0x1
+; MIPS32-OM1: sltu [[T4:.*]],{{.*}},{{.*}}
+; MIPS32-OM1: xori [[T5:.*]],[[T4]],0x1
+; MIPS32-O2: slt [[T3:.*]],[[A_HI]],[[B_HI]]
+; MIPS32-O2: sltu [[T5:.*]],{{.*}},{{.*}}
+; MIPS32: movz [[T3]],[[T5]],[[T1]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T6]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+
 define internal void @icmpLt64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp ult i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
@@ skipping 34 matching lines @@
 ; ARM32-OM1: bne
 ; ARM32-O2: bcs
 ; ARM32: bl
 ; ARM32: cmp
 ; ARM32: sbcs
 ; ARM32-OM1: tst
 ; ARM32-OM1: bne
 ; ARM32-O2: bge
 ; ARM32: bl
 
+; MIPS32-LABEL: icmpLt64
+; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32-O2: sltu [[T2:.*]],[[A_HI]],[[B_HI]]
+; MIPS32-O2: xori [[T3:.*]],[[T2]],0x1
+; MIPS32-O2: sltu [[T4:.*]],{{.*}},{{.*}}
+; MIPS32-O2: xori [[T5:.*]],[[T4]],0x1
+; MIPS32-OM1: sltu [[T3:.*]],[[A_HI]],[[B_HI]]
+; MIPS32-OM1: sltu [[T5:.*]],{{.*}},{{.*}}
+; MIPS32: movz [[T3]],[[T5]],[[T1]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T6]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32-O2: slt [[T2:.*]],[[A_HI]],[[B_HI]]
+; MIPS32-O2: xori [[T3:.*]],[[T2]],0x1
+; MIPS32-O2: sltu [[T4:.*]],{{.*}},{{.*}}
+; MIPS32-O2: xori [[T5:.*]],[[T4]],0x1
+; MIPS32-OM1: slt [[T3:.*]],[[A_HI]],[[B_HI]]
+; MIPS32-OM1: sltu [[T5:.*]],{{.*}},{{.*}}
+; MIPS32: movz [[T3]],[[T5]],[[T1]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T6]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+
 define internal void @icmpLe64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp ule i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
@@ skipping 34 matching lines @@
 ; ARM32-OM1: bne
 ; ARM32-O2: bhi
 ; ARM32: bl
 ; ARM32: cmp
 ; ARM32: sbcs
 ; ARM32-OM1: tst
 ; ARM32-OM1: bne
 ; ARM32-O2: blt
 ; ARM32: bl
 
+; MIPS32-LABEL: icmpLe64
+; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32-OM1: sltu [[T2:.*]],[[B_HI]],[[A_HI]]
+; MIPS32-OM1: xori [[T3:.*]],[[T2]],0x1
+; MIPS32-OM1: sltu [[T4:.*]],{{.*}},{{.*}}
+; MIPS32-OM1: xori [[T5:.*]],[[T4]],0x1
+; MIPS32-O2: sltu [[T3:.*]],[[B_HI]],[[A_HI]]
+; MIPS32-O2: sltu [[T5:.*]],{{.*}},{{.*}}
+; MIPS32: movz [[T3]],[[T5]],[[T1]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T6]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32-OM1: slt [[T2:.*]],[[B_HI]],[[A_HI]]
+; MIPS32-OM1: xori [[T3:.*]],[[T2]],0x1
+; MIPS32-OM1: sltu [[T4:.*]],{{.*}},{{.*}}
+; MIPS32-OM1: xori [[T5:.*]],[[T4]],0x1
+; MIPS32-O2: slt [[T3:.*]],[[B_HI]],[[A_HI]]
+; MIPS32-O2: sltu [[T5:.*]],{{.*}},{{.*}}
+; MIPS32: movz [[T3]],[[T5]],[[T1]]
+; MIPS32-O2: bnez [[T3]],{{.*}}
+; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
+; MIPS32-OM1: beqz [[T6]],{{.*}}
+; MIPS32-OM1: b {{.*}}
+; MIPS32: jal {{.*}}
+; MIPS32-OM1: b {{.*}}
+
 define internal i32 @icmpEq64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp eq i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpEq64Bool
 ; CHECK: jne
 ; CHECK: je
 ;
@@ skipping 630 matching lines @@
   %s = lshr i64 %a, 40
   %t = trunc i64 %s to i32
   %r = sub i32 %t, 1
   ret i32 %r
 ; ARM32-LABEL: subOneToUpperAfterShift
 ; ARM32: subs
 ; ARM32: sbc
 ; ARM32: lsr
 ; ARM32: sub
 }