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Unified Diff: src/arm/assembler-thumb32.cc

Issue 23766038: Thumb2 Backend: 32-bit instruction encoding methods Base URL: HEAD^
Patch Set: Created 7 years, 3 months ago
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Index: src/arm/assembler-thumb32.cc
diff --git a/src/arm/assembler-thumb32.cc b/src/arm/assembler-thumb32.cc
index 2de4044ee59e5d0e528771277135c24b9efb1816..6e9425bbf81672b86cddbf5c4f3d49ad8cbf931c 100644
--- a/src/arm/assembler-thumb32.cc
+++ b/src/arm/assembler-thumb32.cc
@@ -380,6 +380,434 @@ void Assembler::thumb32_instr_at_put(byte* pc, Instr instr) {
*reinterpret_cast<Instr16*>(pc + kInstr16Size) = instr & 0xFFFF;
}
+
+// add imm t3 - mode 1
+void Assembler::add_imm_t3(Register dst, Register src1, SBit s, Condition cond,
+ uint32_t i, uint32_t imm3, uint32_t imm8) {
+ ASSERT(cond == al);
Benedikt Meurer 2013/09/17 08:01:54 Why pass cond if it is constant anyway?
+ emit32(thumb32_mode1(ADD_32_IMM3, s) |
+ thumb32_2reg_thumb_expand_imm(dst, src1, i, imm3, imm8));
+}
+
+
+// add imm t4 - mode 3
+void Assembler::add_imm_t4(Register dst, Register src1, const Operand& src2,
+ SBit s, Condition cond) {
+ ASSERT(cond == al);
Benedikt Meurer 2013/09/17 08:01:54 Same here...
+ // i Rn imm3 Rd imm8
+ emit32(thumb32_mode3(ADD_32_IMM4) |
+ thumb32_2reg_zero_extend_imm_split(src1, dst, src2));
+}
+
+
+// add reg t3 - mode 11
+void Assembler::add_reg_t3(Register dst, Register src1, const Operand& src2,
+ SBit s, Condition cond) {
+ ASSERT(cond == al);
Benedikt Meurer 2013/09/17 08:01:54 And so on...
+ emit32(thumb32_mode11(ADD_32_REG3, s) |
+ thumb32_3reg_shift_imm8(src1, dst, src2));
+}
+
+
+// sub imm t3 - mode 1
+void Assembler::sub_imm_t3(Register dst, Register src1, SBit s, Condition cond,
+ uint32_t i, uint32_t imm3, uint32_t imm8) {
+ ASSERT(cond == al);
+ emit32(thumb32_mode1(SUB_32_IMM3, s) |
+ thumb32_2reg_thumb_expand_imm(dst, src1, i, imm3, imm8) );
+}
+
+
+// sub imm t4 - mode 3
+void Assembler::sub_imm_t4(Register dst, Register src1, const Operand& src2,
+ SBit s, Condition cond) {
+ emit32(thumb32_mode3(SUB_32_IMM4) |
+ thumb32_2reg_zero_extend_imm_split(src1, dst, src2) );
+}
+
+
+// sub reg t3 - mode 11
+void Assembler::sub_reg_t3(Register dst, Register src1, const Operand& src2,
+ SBit s, Condition cond) {
+ ASSERT(cond == al);
+ emit32(thumb32_mode11(SUB_32_REG2 , s) |
+ thumb32_3reg_shift_imm8(src1, dst, src2));
+}
+
+
+// mov imm t2 - mode 1
+void Assembler::mov_imm_t2(Register dst, SBit s, Condition cond,
+ uint32_t i, uint32_t imm3, uint32_t imm8) {
+// note : uses imm4 (replaces Rn)
+ emit32(thumb32_mode1(MOV_32_IMM2, s) |
+ thumb32_2reg_thumb_expand_imm(dst, pc, i, imm3, imm8) );
+}
+
+
+// mov imm t3 - mode 3
+void Assembler::mov_imm_t3(Register dst, const Operand& src, SBit s,
+ Condition cond) {
+ emit32(thumb32_mode3(MOV_32_IMM3) |
+ thumb32_1reg_zero_extend_imm_split_4i38(dst, src.imm32_));
+}
+
+
+// mov reg t2 - mode 11
+void Assembler::mov_reg_t3(Register dst, const Operand& src, SBit s,
+ Condition cond) {
+ ASSERT(cond == al);
+ emit32(thumb32_mode11(MOV_32_REG3, s) |
+ thumb32_3reg_shift_imm8(pc, dst, src));
+}
+
+
+// teq imm t1 - mode 1
+void Assembler::teq_imm_t1(Register src1, Condition cond,
+ uint32_t i, uint32_t imm3, uint32_t imm8) {
+ emit32(thumb32_mode1(TEQ_32_IMM, SetCC) |
+ thumb32_2reg_thumb_expand_imm(pc, src1, i, imm3, imm8) );
+}
+
+
+// teq reg t1 - mode 11
+void Assembler::teq_reg_t1(Register src1, const Operand& src2, Condition cond) {
+ emit32(thumb32_mode11(TEQ_32_REG, SetCC) |
+ thumb32_3reg_shift_imm8(src1, pc, src2));
+}
+
+
+// cmp imm t2 - mode 1
+void Assembler::cmp_imm_t2(Register src1, Condition cond,
+ uint32_t i, uint32_t imm3, uint32_t imm8) {
+ ASSERT(cond == al);
+ emit32(thumb32_mode1(CMP_32_IMM, SetCC) |
+ thumb32_2reg_thumb_expand_imm(pc, src1, i, imm3, imm8) );
+}
+
+
+// cmp reg t3 - mode 11
+void Assembler::cmp_reg_t3(Register src1, const Operand& src2, Condition cond) {
+ ASSERT(cond == al);
+ emit32(thumb32_mode11(CMP_32_REG3, SetCC) |
+ thumb32_3reg_shift_imm8(src1, pc, src2));
+}
+
+
+// lsl imm t2 - mode UNKNOWN
+void Assembler::lsl_imm_t2(Register dst, const Operand& src, SBit s,
+ Condition cond) {
+ ASSERT(cond == al);
+ ASSERT(is_uint5(src.shift_imm_));
+ ASSERT(dst.code() != 13);
+ ASSERT(dst.code() != 15);
+ ASSERT(src.rm_.code() != 13);
+ ASSERT(src.rm_.code() != 15);
+ uint32_t imm3 = src.shift_imm_ >> 2;
+ uint32_t imm2 = src.shift_imm_ & 0x3;
+ ASSERT(imm3 != 0 || imm2 != 0); // see MOV (register)
+ emit32(BH15 | BH14 | BH13 | BH11 | BH9 | BH6 | s | BH3 | BH2 | BH1 | BH0 |
+ imm3*B12 | dst.code()*B8 | imm2*B6 | src.rm_.code());
+}
+
+
+// lsl reg t2 - mode 12
+void Assembler::lsl_reg_t2(Register dst, const Operand& src, SBit s,
+ Condition cond) {
+ ASSERT(cond == al);
+ emit32(thumb32_mode12(LSL_32_REG) | thumb32_3reg_shift(dst, src) | s);
+}
+
+
+// lsr imm t2 - mode UNKNOWN
+void Assembler::lsr_imm_t2(Register dst, const Operand& src, SBit s,
+ Condition cond) {
+ ASSERT(cond == al);
+ ASSERT(is_uint5(src.shift_imm_));
+ ASSERT(dst.code() != 13);
+ ASSERT(dst.code() != 15);
+ ASSERT(src.rm_.code() != 13);
+ ASSERT(src.rm_.code() != 15);
+ uint32_t imm3 = src.shift_imm_ >> 2;
+ uint32_t imm2 = src.shift_imm_ & 0x3;
+ emit32(BH15 | BH14 | BH13 | BH11 | BH9 | BH6 | s | BH3 | BH2 | BH1 | BH0 |
+ imm3*B12 | dst.code()*B8 | imm2*B6 | B4 | src.rm_.code());
+}
+
+
+// lsr reg t2 - mode 12
+void Assembler::lsr_reg_t2(Register dst, const Operand& src, SBit s,
+ Condition cond) {
+ ASSERT(cond == al);
+ emit32(thumb32_mode12(LSR_32_REG) | thumb32_3reg_shift(dst, src) | s);
+}
+
+
+// asr imm t2 - mode UNKNOWN
+void Assembler::asr_imm_t2(Register dst, const Operand& src, SBit s,
+ Condition cond) {
+ ASSERT(is_uint5(src.shift_imm_));
+ ASSERT(dst.code() != 13);
+ ASSERT(dst.code() != 15);
+ ASSERT(src.rm_.code() != 13);
+ ASSERT(src.rm_.code() != 15);
+ uint32_t imm3 = src.shift_imm_ >> 2;
+ uint32_t imm2 = src.shift_imm_ & 0x3;
+ emit32(BH15 | BH14 | BH13 | BH11 | BH9 | BH6 | s | BH3 | BH2 | BH1 | BH0 |
+ imm3*B12 | dst.code()*B8 | imm2*B6 | B5 | src.rm_.code());
+}
+
+
+// ror imm t2 - mode UNKNOWN
+void Assembler::ror_imm_t2(Register dst, const Operand& src, SBit s,
+ Condition cond) {
+ ASSERT(cond == al);
+ ASSERT(is_uint5(src.shift_imm_));
+ ASSERT(dst.code() != 13);
+ ASSERT(dst.code() != 15);
+ ASSERT(src.rm_.code() != 13);
+ ASSERT(src.rm_.code() != 15);
+ uint32_t imm3 = src.shift_imm_ >> 2;
+ uint32_t imm2 = src.shift_imm_ & 0x3;
+ emit32(BH15 | BH14 | BH13 | BH11 | BH9 | BH6 | s | BH3 | BH2 | BH1 | BH0 |
+ imm3*B12 | dst.code()*B8 | imm2*B6 | B5 | B4 | src.rm_.code());
+}
+
+
+// asr reg t2 - mode 12
+void Assembler::asr_reg_t2(Register dst, const Operand& src, SBit s,
+ Condition cond) {
+ emit32(thumb32_mode12(ASR_32_REG) | thumb32_3reg_shift(dst, src) | s);
Benedikt Meurer 2013/09/17 08:01:54 no ASSERT(cond == al) here?
+}
+
+
+// ror reg t2 - mode 12
+void Assembler::ror_reg_t2(Register dst, const Operand& src, SBit s,
+ Condition cond) {
+ ASSERT(cond == al);
+ emit32(thumb32_mode12(ROR_32_REG) | thumb32_3reg_shift(dst, src) | s);
+}
+
+
+// and imm t1 - mode 1
+void Assembler::and_imm_t1(Register dst, Register src1, SBit s, Condition cond,
+ uint32_t i, uint32_t imm3, uint32_t imm8) {
+ ASSERT(cond == al);
+ emit32(thumb32_mode1(AND_32_IMM, s) |
+ thumb32_2reg_thumb_expand_imm(dst, src1, i, imm3, imm8) );
+}
+
+
+// and reg t2 - mode 11
+void Assembler::and_reg_t2(Register dst, Register src1, const Operand& src2,
+ SBit s, Condition cond) {
+// S Rn Rd imm5 type Rm
+ ASSERT(cond == al);
+ emit32(thumb32_mode11(AND_32_REG2, s) |
+ thumb32_3reg_shift_imm8(src1, dst, src2));
+}
+
+
+// eor imm t1 - mode 1
+void Assembler::eor_imm_t1(Register dst, Register src1, SBit s, Condition cond,
+ uint32_t i, uint32_t imm3, uint32_t imm8) {
+ ASSERT(cond == al);
+ emit32(thumb32_mode1(EOR_32_IMM, s) |
+ thumb32_2reg_thumb_expand_imm(dst, src1, i, imm3, imm8));
+}
+
+
+// eor reg t2 - mode 11
+void Assembler::eor_reg_t2(Register dst, Register src1, const Operand& src2,
+ SBit s, Condition cond) {
+// S Rn imm3 Rd immm2 type Rm
+ ASSERT(cond == al);
+ emit32(thumb32_mode11(EOR_32_REG2, s) |
+ thumb32_3reg_shift_imm8(src1, dst, src2));
+}
+
+
+// adc imm t1 - mode 1
+void Assembler::adc_imm_t1(Register dst, Register src1, SBit s, Condition cond,
+ uint32_t i, uint32_t imm3, uint32_t imm8) {
+ ASSERT(cond == al);
+ emit32(thumb32_mode1(ADC_32_IMM , s) |
+ thumb32_2reg_thumb_expand_imm(dst, src1, i, imm3, imm8));
+}
+
+
+// adc reg t2 - mode 11
+void Assembler::adc_reg_t2(Register dst, Register src1, const Operand& src2,
+ SBit s, Condition cond) {
+// S Rn imm3 Rd imm2 type Rm
+ ASSERT(cond == al);
+ emit32(thumb32_mode11(ADC_32_REG2, s) |
+ thumb32_3reg_shift_imm8(src1, dst, src2));
+}
+
+
+// sbc imm t1 - mode 1
+void Assembler::sbc_imm_t1(Register dst, Register src1, SBit s, Condition cond,
+ uint32_t i, uint32_t imm3, uint32_t imm8) {
+ ASSERT(cond == al);
+ emit32(thumb32_mode1(SBC_32_IMM, s) |
+ thumb32_2reg_thumb_expand_imm(dst, src1, i, imm3, imm8));
+}
+
+
+// sbc reg t2 - mode 11
+void Assembler::sbc_reg_t2(Register dst, Register src1, const Operand& src2,
+ SBit s, Condition cond) {
+// S Rn imm3 Rd imm2 type Rm // 3reg
+ ASSERT(cond == al);
+ emit32(thumb32_mode11(SBC_32_REG2, s) |
+ thumb32_3reg_shift_imm8(src1, dst, src2));
+}
+
+
+// rsb imm t1 - mode 1
+void Assembler::rsb_imm_t2(Register dst, Register src1, SBit s, Condition cond,
+ uint32_t i, uint32_t imm3, uint32_t imm8) {
+// S Rn imm3 Rd imm8 // 2reg
+ emit32(thumb32_mode1(RSB_32_IMM, s) |
+ thumb32_2reg_thumb_expand_imm(dst, src1, i, imm3, imm8));
+}
+
+
+// rsb reg t2 - mode 11
+void Assembler::rsb_reg_t1(Register dst, Register src1, const Operand& src2,
+ SBit s, Condition cond) {
+// S Rn imm3 Rd imm2 type Rm // 3reg
+ emit32(thumb32_mode11(RSB_32_REG, s) |
+ thumb32_3reg_shift_imm8(src1, dst, src2));
+}
+
+
+// tst imm t1 - mode 1
+void Assembler::tst_imm_t1(Register src1, Condition cond,
+ uint32_t i, uint32_t imm3, uint32_t imm8) {
+// Rn imm3 imm8 // 1reg
+ emit32(thumb32_mode1(TST_32_IMM, SetCC) |
+ thumb32_2reg_thumb_expand_imm(pc, src1, i, imm3, imm8));
+}
+
+
+// tst reg t2 - mode 11
+void Assembler::tst_reg_t2(Register src1, const Operand& src2, Condition cond) {
+// Rn imm3 imm2 type Rm
+ ASSERT(cond == al);
+ emit32(thumb32_mode11(TST_32_REG2, SetCC) |
+ thumb32_3reg_shift_imm8(src1, pc, src2));
+}
+
+
+// cmn imm t1 - mode 1
+void Assembler::cmn_imm_t1(Register src1, Condition cond,
+ uint32_t i, uint32_t imm3, uint32_t imm8) {
+ ASSERT(cond == al);
+ // SetCC turns on BH4, which is on for cmm immediate T1
+ emit32(thumb32_mode1(CMN_32_IMM, SetCC) |
+ thumb32_2reg_thumb_expand_imm(pc, src1, i, imm3, imm8));
+}
+
+
+// cmn reg t2 - mode 11
+void Assembler::cmn_reg_t2(Register src1, const Operand& src2, Condition cond) {
+// Rn imm3 imm2 type Rm // 2reg
+ ASSERT(cond == al);
+ // SetCC turns on BH4, which is on for cmm register T2
+ emit32(thumb32_mode11(CMN_32_REG2, SetCC) |
+ thumb32_3reg_shift_imm8(src1, pc, src2));
+}
+
+
+// bic imm t1 - mode 1
+void Assembler::bic_imm_t1(Register dst, Register src1, SBit s, Condition cond,
+ uint32_t i, uint32_t imm3, uint32_t imm8) {
+ ASSERT(cond == al);
+ emit32(thumb32_mode1(BIC_32_IMM, s) |
+ thumb32_2reg_thumb_expand_imm(dst, src1, i, imm3, imm8));
+}
+
+
+// bic reg t2 - mode 11
+void Assembler::bic_reg_t2(Register dst, Register src1, const Operand& src2,
+ SBit s, Condition cond) {
+// S Rn imm3 Rd imm2 type Rm // 3reg
+ ASSERT(cond == al);
+ emit32(thumb32_mode11(BIC_32_REG2 , s) |
+ thumb32_3reg_shift_imm8(src1, dst, src2));
+}
+
+
+// mul t2 - mode 16
+void Assembler::mul_t2(Register dst, Register src1, Register src2,
+ SBit s, Condition cond) {
+ ASSERT(cond == al);
+ emit32(thumb32_mode16(MUL_32) | thumb32_4reg(dst, src1, src2, pc));
+}
+
+
+// mvn imm t1 - mode 1
+void Assembler::mvn_imm_t1(Register dst, SBit s, Condition cond,
+ uint32_t i, uint32_t imm3, uint32_t imm8) {
+ ASSERT(cond == al);
+ emit32(thumb32_mode1(MVN_32_IMM, s) |
+ thumb32_2reg_thumb_expand_imm(dst, pc, i, imm3, imm8));
+}
+
+
+// mvn reg t2 - mode 11
+void Assembler::mvn_reg_t2(Register dst, const Operand& src, SBit s,
+ Condition cond) {
+ ASSERT(cond == al);
+ emit32(thumb32_mode11(MVN_32_REG2, s) |
+ thumb32_3reg_shift_imm8(pc, dst, src));
+}
+
+
+// orr imm t1 - mode 1
+void Assembler::orr_imm_t1(Register dst, Register src1, SBit s, Condition cond,
+ uint32_t i, uint32_t imm3, uint32_t imm8) {
+ ASSERT(cond == al);
+ emit32(thumb32_mode1(ORR_32_IMM, s) |
+ thumb32_2reg_thumb_expand_imm(dst, src1, i, imm3, imm8));
+}
+
+
+// orr reg t2 - mode 11
+void Assembler::orr_reg_t2(Register dst, Register src1, const Operand& src2,
+ SBit s, Condition cond) {
+ ASSERT(cond == al);
+ emit32(thumb32_mode11(ORR_32_REG2, s) |
+ thumb32_3reg_shift_imm8(src1, dst, src2));
+}
+
+
+// Mode 3, note:
+// bfi imm t1 - mode 3 is included in bfi()
+// bfc imm t1 - mode 3 is included in bfc()
+// usat imm t1 - mode 3 is included in usat()
+// ubfx imm t1 - mode 3 is included in ubfx()
+// Mode 15
+// clz t1 included in clz()
+
+
+// ldrd imm t1 - has 2
+void Assembler::ldrd_imm_t1(Register dst1, Register dst2,
+ const MemOperand& src) {
+ // Note: BH5 is both op2's high bit and W; LDRD_32_IMM_OP2 sets W on
+ // so created _x1
+ emit32(thumb32_mode6(LDRD_32_IMM, LDRD_32_IMM_OP2_x1) |
+ thumb32_3reg_zero_extend_imm8(dst1, dst2, src));
+}
+
+
+void Assembler::strd_imm_t1(Register src1, Register src2,
+ const MemOperand& dst) {
+ emit32(thumb32_mode6(STRD_32_IMM2, STRD_32_IMM2_OP2) |
+ thumb32_3reg_zero_extend_imm8(src1, src2, dst));
+}
+
} } // namespace v8::internal
#endif // V8_TARGET_ARCH_ARM
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