| Index: src/arm/assembler-arm.h
|
| diff --git a/src/arm/assembler-arm.h b/src/arm/assembler-arm.h
|
| index 6fb692f22ef4616786f8740d93eaae44e484480d..3223f827e101a1f54312725bafe98ab6463ace47 100644
|
| --- a/src/arm/assembler-arm.h
|
| +++ b/src/arm/assembler-arm.h
|
| @@ -842,9 +842,17 @@ class Assembler : public AssemblerBase {
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|
|
| void and_(Register dst, Register src1, const Operand& src2,
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| SBit s = LeaveCC, Condition cond = al);
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| + void and_imm_t1(Register dst, Register src1, SBit s, Condition cond,
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| + uint32_t i, uint32_t imm3, uint32_t imm8);
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| + void and_reg_t2(Register dst, Register src1, const Operand& src2,
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| + SBit s, Condition cond);
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|
|
| void eor(Register dst, Register src1, const Operand& src2,
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| SBit s = LeaveCC, Condition cond = al);
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| + void eor_imm_t1(Register dst, Register src1, SBit s, Condition cond,
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| + uint32_t i, uint32_t imm3, uint32_t imm8);
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| + void eor_reg_t2(Register dst, Register src1, const Operand& src2,
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| + SBit s, Condition cond);
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|
|
| void sub(Register dst, Register src1, const Operand& src2,
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| SBit s = LeaveCC, Condition cond = al);
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| @@ -852,9 +860,19 @@ class Assembler : public AssemblerBase {
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| SBit s = LeaveCC, Condition cond = al) {
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| sub(dst, src1, Operand(src2), s, cond);
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| }
|
| + void sub_imm_t3(Register dst, Register src1, SBit s, Condition cond,
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| + uint32_t i, uint32_t imm3, uint32_t imm8);
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| + void sub_imm_t4(Register dst, Register src1, const Operand& src2,
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| + SBit s, Condition cond);
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| + void sub_reg_t3(Register dst, Register src1, const Operand& src2,
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| + SBit s, Condition cond);
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|
|
| void rsb(Register dst, Register src1, const Operand& src2,
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| SBit s = LeaveCC, Condition cond = al);
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| + void rsb_imm_t2(Register dst, Register src1, SBit s, Condition cond,
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| + uint32_t i, uint32_t imm3, uint32_t imm8);
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| + void rsb_reg_t1(Register dst, Register src1, const Operand& src2,
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| + SBit s, Condition cond);
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|
|
| void add(Register dst, Register src1, const Operand& src2,
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| SBit s = LeaveCC, Condition cond = al);
|
| @@ -862,12 +880,26 @@ class Assembler : public AssemblerBase {
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| SBit s = LeaveCC, Condition cond = al) {
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| add(dst, src1, Operand(src2), s, cond);
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| }
|
| + void add_imm_t3(Register dst, Register src1, SBit s, Condition cond,
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| + uint32_t i, uint32_t imm3, uint32_t imm8);
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| + void add_imm_t4(Register dst, Register src1, const Operand& src2,
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| + SBit s, Condition cond);
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| + void add_reg_t3(Register dst, Register src1, const Operand& src2,
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| + SBit s, Condition cond);
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|
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| void adc(Register dst, Register src1, const Operand& src2,
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| SBit s = LeaveCC, Condition cond = al);
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| + void adc_imm_t1(Register dst, Register src1, SBit s, Condition cond,
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| + uint32_t i, uint32_t imm3, uint32_t imm8);
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| + void adc_reg_t2(Register dst, Register src1, const Operand& src2,
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| + SBit s, Condition cond);
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|
|
| void sbc(Register dst, Register src1, const Operand& src2,
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| SBit s = LeaveCC, Condition cond = al);
|
| + void sbc_imm_t1(Register dst, Register src1, SBit s, Condition cond,
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| + uint32_t i, uint32_t imm3, uint32_t imm8);
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| + void sbc_reg_t2(Register dst, Register src1, const Operand& src2,
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| + SBit s, Condition cond);
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|
|
| void rsc(Register dst, Register src1, const Operand& src2,
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| SBit s = LeaveCC, Condition cond = al);
|
| @@ -876,16 +908,28 @@ class Assembler : public AssemblerBase {
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| void tst(Register src1, Register src2, Condition cond = al) {
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| tst(src1, Operand(src2), cond);
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| }
|
| + void tst_imm_t1(Register src1, Condition cond,
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| + uint32_t i, uint32_t imm3, uint32_t imm8);
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| + void tst_reg_t2(Register src1, const Operand& src2, Condition cond);
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|
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| void teq(Register src1, const Operand& src2, Condition cond = al);
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| + void teq_imm_t1(Register src1, Condition cond,
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| + uint32_t i, uint32_t imm3, uint32_t imm8);
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| + void teq_reg_t1(Register src1, const Operand& src2, Condition cond);
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|
|
| void cmp(Register src1, const Operand& src2, Condition cond = al);
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| void cmp(Register src1, Register src2, Condition cond = al) {
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| cmp(src1, Operand(src2), cond);
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| }
|
| + void cmp_imm_t2(Register src1, Condition cond,
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| + uint32_t i, uint32_t imm3, uint32_t imm8);
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| + void cmp_reg_t3(Register src1, const Operand& src2, Condition cond);
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| void cmp_raw_immediate(Register src1, int raw_immediate, Condition cond = al);
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|
|
| void cmn(Register src1, const Operand& src2, Condition cond = al);
|
| + void cmn_imm_t1(Register src1, Condition cond,
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| + uint32_t i, uint32_t imm3, uint32_t imm8);
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| + void cmn_reg_t2(Register src1, const Operand& src2, Condition cond);
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|
|
| void orr(Register dst, Register src1, const Operand& src2,
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| SBit s = LeaveCC, Condition cond = al);
|
| @@ -893,12 +937,31 @@ class Assembler : public AssemblerBase {
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| SBit s = LeaveCC, Condition cond = al) {
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| orr(dst, src1, Operand(src2), s, cond);
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| }
|
| + void orr_imm_t1(Register dst, Register src1, SBit s, Condition cond,
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| + uint32_t i, uint32_t imm3, uint32_t imm8);
|
| + void orr_reg_t2(Register dst, Register src1, const Operand& src2,
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| + SBit s, Condition cond);
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|
|
| void mov(Register dst, const Operand& src,
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| SBit s = LeaveCC, Condition cond = al);
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| void mov(Register dst, Register src, SBit s = LeaveCC, Condition cond = al) {
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| mov(dst, Operand(src), s, cond);
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| }
|
| + void mov_imm_t2(Register dst, SBit s, Condition cond,
|
| + uint32_t i, uint32_t imm3, uint32_t imm8);
|
| + void mov_imm_t3(Register dst, const Operand& src,
|
| + SBit s, Condition cond);
|
| + void mov_reg_t3(Register dst, const Operand& src,
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| + SBit s, Condition cond);
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| +
|
| + void lsl_imm_t2(Register dst, const Operand& src, SBit s, Condition cond);
|
| + void lsl_reg_t2(Register dst, const Operand& src, SBit s, Condition cond);
|
| + void lsr_imm_t2(Register dst, const Operand& src, SBit s, Condition cond);
|
| + void lsr_reg_t2(Register dst, const Operand& src, SBit s, Condition cond);
|
| + void asr_imm_t2(Register dst, const Operand& src, SBit s, Condition cond);
|
| + void asr_reg_t2(Register dst, const Operand& src, SBit s, Condition cond);
|
| + void ror_imm_t2(Register dst, const Operand& src, SBit s, Condition cond);
|
| + void ror_reg_t2(Register dst, const Operand& src, SBit s, Condition cond);
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|
|
| // Load the position of the label relative to the generated code object
|
| // pointer in a register.
|
| @@ -913,9 +976,17 @@ class Assembler : public AssemblerBase {
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|
|
| void bic(Register dst, Register src1, const Operand& src2,
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| SBit s = LeaveCC, Condition cond = al);
|
| + void bic_imm_t1(Register dst, Register src1, SBit s, Condition cond,
|
| + uint32_t i, uint32_t imm3, uint32_t imm8);
|
| + void bic_reg_t2(Register dst, Register src1, const Operand& src2,
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| + SBit s, Condition cond);
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|
|
| void mvn(Register dst, const Operand& src,
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| SBit s = LeaveCC, Condition cond = al);
|
| + void mvn_imm_t1(Register dst, SBit s, Condition cond,
|
| + uint32_t i, uint32_t imm3, uint32_t imm8);
|
| + void mvn_reg_t2(Register dst, const Operand& src,
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| + SBit s, Condition cond);
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|
|
| // Multiply instructions
|
|
|
| @@ -930,6 +1001,8 @@ class Assembler : public AssemblerBase {
|
|
|
| void mul(Register dst, Register src1, Register src2,
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| SBit s = LeaveCC, Condition cond = al);
|
| + void mul_t2(Register dst, Register src1, Register src2,
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| + SBit s, Condition cond);
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|
|
| void smlal(Register dstL, Register dstH, Register src1, Register src2,
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| SBit s = LeaveCC, Condition cond = al);
|
| @@ -1009,9 +1082,15 @@ class Assembler : public AssemblerBase {
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| void ldrd(Register dst1,
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| Register dst2,
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| const MemOperand& src, Condition cond = al);
|
| + void ldrd_imm_t1(Register dst1,
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| + Register dst2,
|
| + const MemOperand& src);
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| void strd(Register src1,
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| Register src2,
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| const MemOperand& dst, Condition cond = al);
|
| + void strd_imm_t1(Register src1,
|
| + Register src2,
|
| + const MemOperand& dst);
|
|
|
| // Preload instructions
|
| void pld(const MemOperand& address);
|
|
|