Thumb2 Backend: 32-bit instruction encoding methods

src/arm/assembler-arm.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 824 matching lines @@
   }
   void b(Condition cond, Label* L)  { b(branch_offset(L, cond == al), cond); }
   void bl(Label* L, Condition cond = al)  { bl(branch_offset(L, false), cond); }
   void bl(Condition cond, Label* L)  { bl(branch_offset(L, false), cond); }
   void blx(Label* L)  { blx(branch_offset(L, false)); }  // v5 and above
 
   // Data-processing instructions
 
   void and_(Register dst, Register src1, const Operand& src2,
             SBit s = LeaveCC, Condition cond = al);
+  void and_imm_t1(Register dst, Register src1, SBit s, Condition cond,
+                  uint32_t i, uint32_t imm3, uint32_t imm8);
+  void and_reg_t2(Register dst, Register src1, const Operand& src2,
+                  SBit s, Condition cond);
 
   void eor(Register dst, Register src1, const Operand& src2,
            SBit s = LeaveCC, Condition cond = al);
+  void eor_imm_t1(Register dst, Register src1, SBit s, Condition cond,
+                  uint32_t i, uint32_t imm3, uint32_t imm8);
+  void eor_reg_t2(Register dst, Register src1, const Operand& src2,
+                  SBit s, Condition cond);
 
   void sub(Register dst, Register src1, const Operand& src2,
            SBit s = LeaveCC, Condition cond = al);
   void sub(Register dst, Register src1, Register src2,
            SBit s = LeaveCC, Condition cond = al) {
     sub(dst, src1, Operand(src2), s, cond);
   }
+  void sub_imm_t3(Register dst, Register src1, SBit s, Condition cond,
+                  uint32_t i, uint32_t imm3, uint32_t imm8);
+  void sub_imm_t4(Register dst, Register src1, const Operand& src2,
+                  SBit s, Condition cond);
+  void sub_reg_t3(Register dst, Register src1, const Operand& src2,
+                  SBit s, Condition cond);
 
   void rsb(Register dst, Register src1, const Operand& src2,
            SBit s = LeaveCC, Condition cond = al);
+  void rsb_imm_t2(Register dst, Register src1, SBit s, Condition cond,
+                  uint32_t i, uint32_t imm3, uint32_t imm8);
+  void rsb_reg_t1(Register dst, Register src1, const Operand& src2,
+                  SBit s, Condition cond);
 
   void add(Register dst, Register src1, const Operand& src2,
            SBit s = LeaveCC, Condition cond = al);
   void add(Register dst, Register src1, Register src2,
            SBit s = LeaveCC, Condition cond = al) {
     add(dst, src1, Operand(src2), s, cond);
   }
+  void add_imm_t3(Register dst, Register src1, SBit s, Condition cond,
+                  uint32_t i, uint32_t imm3, uint32_t imm8);
+  void add_imm_t4(Register dst, Register src1, const Operand& src2,
+                  SBit s, Condition cond);
+  void add_reg_t3(Register dst, Register src1, const Operand& src2,
+                  SBit s, Condition cond);
 
   void adc(Register dst, Register src1, const Operand& src2,
            SBit s = LeaveCC, Condition cond = al);
+  void adc_imm_t1(Register dst, Register src1, SBit s, Condition cond,
+                  uint32_t i, uint32_t imm3, uint32_t imm8);
+  void adc_reg_t2(Register dst, Register src1, const Operand& src2,
+                  SBit s, Condition cond);
 
   void sbc(Register dst, Register src1, const Operand& src2,
            SBit s = LeaveCC, Condition cond = al);
+  void sbc_imm_t1(Register dst, Register src1, SBit s, Condition cond,
+                  uint32_t i, uint32_t imm3, uint32_t imm8);
+  void sbc_reg_t2(Register dst, Register src1, const Operand& src2,
+                  SBit s, Condition cond);
 
   void rsc(Register dst, Register src1, const Operand& src2,
            SBit s = LeaveCC, Condition cond = al);
 
   void tst(Register src1, const Operand& src2, Condition cond = al);
   void tst(Register src1, Register src2, Condition cond = al) {
     tst(src1, Operand(src2), cond);
   }
+  void tst_imm_t1(Register src1, Condition cond,
+                  uint32_t i, uint32_t imm3, uint32_t imm8);
+  void tst_reg_t2(Register src1, const Operand& src2, Condition cond);
 
   void teq(Register src1, const Operand& src2, Condition cond = al);
+  void teq_imm_t1(Register src1, Condition cond,
+                  uint32_t i, uint32_t imm3, uint32_t imm8);
+  void teq_reg_t1(Register src1, const Operand& src2, Condition cond);
 
   void cmp(Register src1, const Operand& src2, Condition cond = al);
   void cmp(Register src1, Register src2, Condition cond = al) {
     cmp(src1, Operand(src2), cond);
   }
+  void cmp_imm_t2(Register src1, Condition cond,
+                  uint32_t i, uint32_t imm3, uint32_t imm8);
+  void cmp_reg_t3(Register src1, const Operand& src2, Condition cond);
   void cmp_raw_immediate(Register src1, int raw_immediate, Condition cond = al);
 
   void cmn(Register src1, const Operand& src2, Condition cond = al);
+  void cmn_imm_t1(Register src1, Condition cond,
+                  uint32_t i, uint32_t imm3, uint32_t imm8);
+  void cmn_reg_t2(Register src1, const Operand& src2, Condition cond);
 
   void orr(Register dst, Register src1, const Operand& src2,
            SBit s = LeaveCC, Condition cond = al);
   void orr(Register dst, Register src1, Register src2,
            SBit s = LeaveCC, Condition cond = al) {
     orr(dst, src1, Operand(src2), s, cond);
   }
+  void orr_imm_t1(Register dst, Register src1, SBit s, Condition cond,
+                  uint32_t i, uint32_t imm3, uint32_t imm8);
+  void orr_reg_t2(Register dst, Register src1, const Operand& src2,
+                  SBit s, Condition cond);
 
   void mov(Register dst, const Operand& src,
            SBit s = LeaveCC, Condition cond = al);
   void mov(Register dst, Register src, SBit s = LeaveCC, Condition cond = al) {
     mov(dst, Operand(src), s, cond);
   }
+  void mov_imm_t2(Register dst, SBit s, Condition cond,
+                  uint32_t i, uint32_t imm3, uint32_t imm8);
+  void mov_imm_t3(Register dst, const Operand& src,
+                  SBit s, Condition cond);
+  void mov_reg_t3(Register dst, const Operand& src,
+                  SBit s, Condition cond);
+
+  void lsl_imm_t2(Register dst, const Operand& src, SBit s, Condition cond);
+  void lsl_reg_t2(Register dst, const Operand& src, SBit s, Condition cond);
+  void lsr_imm_t2(Register dst, const Operand& src, SBit s, Condition cond);
+  void lsr_reg_t2(Register dst, const Operand& src, SBit s, Condition cond);
+  void asr_imm_t2(Register dst, const Operand& src, SBit s, Condition cond);
+  void asr_reg_t2(Register dst, const Operand& src, SBit s, Condition cond);
+  void ror_imm_t2(Register dst, const Operand& src, SBit s, Condition cond);
+  void ror_reg_t2(Register dst, const Operand& src, SBit s, Condition cond);
 
   // Load the position of the label relative to the generated code object
   // pointer in a register.
   void mov_label_offset(Register dst, Label* label);
 
   // ARMv7 instructions for loading a 32 bit immediate in two instructions.
   // This may actually emit a different mov instruction, but on an ARMv7 it
   // is guaranteed to only emit one instruction.
   void movw(Register reg, uint32_t immediate, Condition cond = al);
   // The constant for movt should be in the range 0-0xffff.
   void movt(Register reg, uint32_t immediate, Condition cond = al);
 
   void bic(Register dst, Register src1, const Operand& src2,
            SBit s = LeaveCC, Condition cond = al);
+  void bic_imm_t1(Register dst, Register src1, SBit s, Condition cond,
+                  uint32_t i, uint32_t imm3, uint32_t imm8);
+  void bic_reg_t2(Register dst, Register src1, const Operand& src2,
+                  SBit s, Condition cond);
 
   void mvn(Register dst, const Operand& src,
            SBit s = LeaveCC, Condition cond = al);
+  void mvn_imm_t1(Register dst, SBit s, Condition cond,
+                  uint32_t i, uint32_t imm3, uint32_t imm8);
+  void mvn_reg_t2(Register dst, const Operand& src,
+                  SBit s, Condition cond);
 
   // Multiply instructions
 
   void mla(Register dst, Register src1, Register src2, Register srcA,
            SBit s = LeaveCC, Condition cond = al);
 
   void mls(Register dst, Register src1, Register src2, Register srcA,
            Condition cond = al);
 
   void sdiv(Register dst, Register src1, Register src2,
             Condition cond = al);
 
   void mul(Register dst, Register src1, Register src2,
            SBit s = LeaveCC, Condition cond = al);
+  void mul_t2(Register dst, Register src1, Register src2,
+              SBit s, Condition cond);
 
   void smlal(Register dstL, Register dstH, Register src1, Register src2,
              SBit s = LeaveCC, Condition cond = al);
 
   void smull(Register dstL, Register dstH, Register src1, Register src2,
              SBit s = LeaveCC, Condition cond = al);
 
   void umlal(Register dstL, Register dstH, Register src1, Register src2,
              SBit s = LeaveCC, Condition cond = al);
 
@@ skipping 59 matching lines @@
   void str(Register src, const MemOperand& dst, Condition cond = al);
   void ldrb(Register dst, const MemOperand& src, Condition cond = al);
   void strb(Register src, const MemOperand& dst, Condition cond = al);
   void ldrh(Register dst, const MemOperand& src, Condition cond = al);
   void strh(Register src, const MemOperand& dst, Condition cond = al);
   void ldrsb(Register dst, const MemOperand& src, Condition cond = al);
   void ldrsh(Register dst, const MemOperand& src, Condition cond = al);
   void ldrd(Register dst1,
             Register dst2,
             const MemOperand& src, Condition cond = al);
+  void ldrd_imm_t1(Register dst1,
+                   Register dst2,
+                   const MemOperand& src);
   void strd(Register src1,
             Register src2,
             const MemOperand& dst, Condition cond = al);
+  void strd_imm_t1(Register src1,
+                   Register src2,
+                   const MemOperand& dst);
 
   // Preload instructions
   void pld(const MemOperand& address);
 
   // Load/Store multiple instructions
   void ldm(BlockAddrMode am, Register base, RegList dst, Condition cond = al);
   void stm(BlockAddrMode am, Register base, RegList src, Condition cond = al);
 
   // Exception-generating instructions and debugging support
   void stop(const char* msg,
@@ skipping 662 matching lines @@
  public:
   explicit EnsureSpace(Assembler* assembler) {
     assembler->CheckBuffer();
   }
 };
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_ARM_ASSEMBLER_ARM_H_