Subzero, MIPS32: SRAV instruction encoding

src/IceAssemblerMIPS32.cpp

Index: src/IceAssemblerMIPS32.cpp
diff --git a/src/IceAssemblerMIPS32.cpp b/src/IceAssemblerMIPS32.cpp
index 00ef9feb5d9f053d1158e3895edf4aea2944baee..ce690426746ffa73d892fcaeee110cc25ed91476 100644
--- a/src/IceAssemblerMIPS32.cpp
+++ b/src/IceAssemblerMIPS32.cpp
@@ -845,6 +845,12 @@ void AssemblerMIPS32::srl(const Operand *OpRd, const Operand *OpRt,
   emitRdRtSa(Opcode, OpRd, OpRt, Sa, "srl");
 }
 
+void AssemblerMIPS32::srav(const Operand *OpRd, const Operand *OpRt,
+                           const Operand *OpRs) {
+  static constexpr IValueT Opcode = 0x00000007;
+  emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "srav");
+}
+
 void AssemblerMIPS32::srlv(const Operand *OpRd, const Operand *OpRt,
                            const Operand *OpRs) {
   static constexpr IValueT Opcode = 0x00000006;