Subzero, MIPS32: SRAV instruction encoding

src/IceAssemblerMIPS32.cpp

 //===- subzero/src/IceAssemblerMIPS32.cpp - MIPS32 Assembler --------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 827 matching lines @@
   static constexpr IValueT Opcode = 0x00000003;
   emitRdRtSa(Opcode, OpRd, OpRt, Sa, "sra");
 }
 
 void AssemblerMIPS32::srl(const Operand *OpRd, const Operand *OpRt,
                           const uint32_t Sa) {
   static constexpr IValueT Opcode = 0x00000002;
   emitRdRtSa(Opcode, OpRd, OpRt, Sa, "srl");
 }
 
+void AssemblerMIPS32::srav(const Operand *OpRd, const Operand *OpRt,
+                           const Operand *OpRs) {
+  static constexpr IValueT Opcode = 0x00000007;
+  emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "srav");
+}
+
 void AssemblerMIPS32::srlv(const Operand *OpRd, const Operand *OpRt,
                            const Operand *OpRs) {
   static constexpr IValueT Opcode = 0x00000006;
   emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "srlv");
 }
 
 void AssemblerMIPS32::sub_d(const Operand *OpFd, const Operand *OpFs,
                             const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000001;
   emitCOP1FmtFtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "sub.d");
@@ skipping 156 matching lines @@
     emitBr(Cond, OpRs, OpRtNone, Dest);
     return;
   }
   const IOffsetT Position = Buffer.size();
   emitBr(Cond, OpRs, OpRtNone, TargetLabel->getEncodedPosition());
   TargetLabel->linkTo(*this, Position);
 }
 
 } // end of namespace MIPS32
 } // end of namespace Ice