[Subzero][MIPS] Implement 64-bit integer compare operations

tests_lit/llvm2ice_tests/64bit.pnacl.ll

Index: tests_lit/llvm2ice_tests/64bit.pnacl.ll
diff --git a/tests_lit/llvm2ice_tests/64bit.pnacl.ll b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
index 5ca38a9c7d4e100c88374d1477795b6963222187..5a41ae85219500b6d4ff132a7f1437c110adcb0e 100644
--- a/tests_lit/llvm2ice_tests/64bit.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
@@ -1604,6 +1604,12 @@ entry:
 ; ARM32: mov
 ; ARM32: moveq
 
+; MIPS32-LABEL: icmpEq64Bool
+; MIPS32: xor	[[T1:.*]],{{.*}},{{.*}}
+; MIPS32: xor	[[T2:.*]],{{.*}},{{.*}}
+; MIPS32: or	[[T3:.*]],[[T1]],[[T2]]
+; MIPS32: sltiu	{{.*}},[[T3]],1
+
 define internal i32 @icmpNe64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp ne i64 %a, %b
@@ -1622,6 +1628,12 @@ entry:
 ; ARM32: mov
 ; ARM32: movne
 
+; MIPS32-LABEL: icmpNe64Bool
+; MIPS32: xor   [[T1:.*]],{{.*}},{{.*}}
+; MIPS32: xor   [[T2:.*]],{{.*}},{{.*}}
+; MIPS32: or    [[T3:.*]],[[T1]],[[T2]]
+; MIPS32: sltu {{.*}},zero,[[T3]]
+
 define internal i32 @icmpSgt64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp sgt i64 %a, %b
@@ -1648,6 +1660,15 @@ entry:
 ; ARM32: sbcs
 ; ARM32: movlt
 
+; MIPS32-LABEL: icmpSgt64Bool
+; MIPS32: xor	[[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32: slt	[[T2:.*]],{{.*}},{{.*}}
+; MIPS32: sltu	[[T3:.*]],{{.*}},{{.*}}
+; MIPS32: movz	[[T2]],[[T3]],[[T1]]
+; MIPS32-O2: move	{{.*}},[[T2]]

[Jim Stichnoth, 2016/09/27 13:45:35]

The "MIPS32-O2" and "MIPS32-OM1" lines don't actually do anything because MIPS32
is only being tested with "--check-prefix MIPS32".

It would be great if you could add change this file so that both O2 and Om1 are
being tested, but it's possible that could end up being too big for this CL.

Otherwise, the simplest may be to add "--check-prefix MIPS32-O2" to the RUN
command and handle MIPS32-OM1 later.

[sagar.thakur, 2016/09/28 08:23:23]

Done. I will add RUN command line for Om1 in a separate CL.

+; MIPS32-OM1: sw	[[T2]],[[MEM:.*]]
+; MIPS32-OM1: lb	{{.*}},[[MEM]]
+
 define internal i32 @icmpUgt64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp ugt i64 %a, %b
@@ -1674,6 +1695,15 @@ entry:
 ; ARM32: cmpeq
 ; ARM32: movhi
 
+; MIPS32-LABEL: icmpUgt64Bool
+; MIPS32: xor	[[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32: sltu	[[T2:.*]],[[B_HI]],[[A_HI]]
+; MIPS32: sltu	[[T3:.*]],{{.*}},{{.*}}
+; MIPS32: movz	[[T2]],[[T3]],[[T1]]
+; MIPS32-O2: move	{{.*}},[[T2]]
+; MIPS32-OM1: sw	[[T2]],[[MEM:.*]]
+; MIPS32-OM1: lb	{{.*}},[[MEM]]
+
 define internal i32 @icmpSge64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp sge i64 %a, %b
@@ -1700,6 +1730,17 @@ entry:
 ; ARM32: sbcs
 ; ARM32: movge
 
+; MIPS32-LABEL: icmpSge64Bool
+; MIPS32: xor	[[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32: slt	[[T2:.*]],[[A_HI]],[[B_HI]]
+; MIPS32: xori	[[T3:.*]],[[T2]],0x1
+; MIPS32: sltu	[[T4:.*]],{{.*}},{{.*}}
+; MIPS32: xori	[[T5:.*]],[[T4]],0x1
+; MIPS32: movz	[[T6:.*]],[[T5]],[[T1]]
+; MIPS32-O2: move       {{.*}},[[T3]]
+; MIPS32-OM1: sw        [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb        {{.*}},[[MEM]]
+
 define internal i32 @icmpUge64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp uge i64 %a, %b
@@ -1726,6 +1767,17 @@ entry:
 ; ARM32: cmpeq
 ; ARM32: movcs
 
+; MIPS32-LABEL: icmpUge64Bool
+; MIPS32: xor	[[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32: sltu	[[T2:.*]],[[A_HI]],[[B_HI]]
+; MIPS32: xori	[[T3:.*]],[[T2]],0x1
+; MIPS32: sltu	[[T4:.*]],{{.*}},{{.*}}
+; MIPS32: xori	[[T5:.*]],[[T4]],0x1
+; MIPS32: movz	[[T6:.*]],[[T5]],[[T1]]
+; MIPS32-O2: move	{{.*}},[[T3]]
+; MIPS32-OM1: sw	[[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb	{{.*}},[[MEM]]
+
 define internal i32 @icmpSlt64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp slt i64 %a, %b
@@ -1752,6 +1804,15 @@ entry:
 ; ARM32: sbcs
 ; ARM32: movlt
 
+; MIPS32-LABEL: icmpSlt64Bool
+; MIPS32: xor	[[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32: slt	[[T2:.*]],[[A_HI]],[[B_HI]]
+; MIPS32: sltu	[[T3:.*]],{{.*}},{{.*}}
+; MIPS32: movz	[[T2:.*]],[[T3]],[[T1]]
+; MIPS32-O2: move	{{.*}},[[T2]]
+; MIPS32-OM1: sw	[[T2]],[[MEM:.*]]
+; MIPS32-OM1: lb	{{.*}},[[MEM]]
+
 define internal i32 @icmpUlt64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp ult i64 %a, %b
@@ -1778,6 +1839,15 @@ entry:
 ; ARM32: cmpeq
 ; ARM32: movcc
 
+; MIPS32-LABEL: icmpUlt64Bool
+; MIPS32: xor	[[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32: sltu	[[T2:.*]],[[A_HI]],[[B_HI]]
+; MIPS32: sltu	[[T3:.*]],{{.*}},{{.*}}
+; MIPS32: movz	[[T2:.*]],[[T3]],[[T1]]
+; MIPS32-O2: move	{{.*}},[[T2]]
+; MIPS32-OM1: sw	[[T2]],[[MEM:.*]]
+; MIPS32-OM1: lb	{{.*}},[[MEM]]
+
 define internal i32 @icmpSle64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp sle i64 %a, %b
@@ -1804,6 +1874,17 @@ entry:
 ; ARM32: sbcs
 ; ARM32: movge
 
+; MIPS32-LABEL: icmpSle64Bool
+; MIPS32: xor	[[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32: slt	[[T2:.*]],[[B_HI]],[[A_HI]]
+; MIPS32: xori	[[T3:.*]],[[T2]],0x1
+; MIPS32: sltu	[[T4:.*]],{{.*}},{{.*}}
+; MIPS32: xori	[[T5:.*]],[[T4]],0x1
+; MIPS32: movz	[[T6:.*]],[[T5]],[[T1]]
+; MIPS32-O2: move	{{.*}},[[T3]]
+; MIPS32-OM1: sw	[[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb	{{.*}},[[MEM]]
+
 define internal i32 @icmpUle64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp ule i64 %a, %b
@@ -1830,6 +1911,17 @@ entry:
 ; ARM32: cmpeq
 ; ARM32: movls
 
+; MIPS32-LABEL: icmpUle64Bool
+; MIPS32: xor	[[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32: sltu	[[T2:.*]],[[B_HI]],[[A_HI]]
+; MIPS32: xori	[[T3:.*]],[[T2]],0x1
+; MIPS32: sltu	[[T4:.*]],{{.*}},{{.*}}
+; MIPS32: xori	[[T5:.*]],[[T4]],0x1
+; MIPS32: movz	[[T6:.*]],[[T5]],[[T1]]
+; MIPS32-O2: move	{{.*}},[[T3]]
+; MIPS32-OM1: sw	[[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb	{{.*}},[[MEM]]
+
 define internal i64 @load64(i32 %a) {
 entry:
   %__1 = inttoptr i32 %a to i64*