[Subzero][MIPS] Implement 64-bit integer compare operations

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
@@ skipping 1586 matching lines @@
 ; CHECK: je
 ;
 ; OPTM1-LABEL: icmpEq64Bool
 ; OPTM1: jne
 ; OPTM1: je
 
 ; ARM32-LABEL: icmpEq64Bool
 ; ARM32: mov
 ; ARM32: moveq
 
+; MIPS32-LABEL: icmpEq64Bool
+; MIPS32: xor   [[T1:.*]],{{.*}},{{.*}}
+; MIPS32: xor   [[T2:.*]],{{.*}},{{.*}}
+; MIPS32: or    [[T3:.*]],[[T1]],[[T2]]
+; MIPS32: sltiu {{.*}},[[T3]],1
+
 define internal i32 @icmpNe64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp ne i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpNe64Bool
 ; CHECK: jne
 ; CHECK: jne
 ;
 ; OPTM1-LABEL: icmpNe64Bool
 ; OPTM1: jne
 ; OPTM1: jne
 
 ; ARM32-LABEL: icmpNe64Bool
 ; ARM32: mov
 ; ARM32: movne
 
+; MIPS32-LABEL: icmpNe64Bool
+; MIPS32: xor   [[T1:.*]],{{.*}},{{.*}}
+; MIPS32: xor   [[T2:.*]],{{.*}},{{.*}}
+; MIPS32: or    [[T3:.*]],[[T1]],[[T2]]
+; MIPS32: sltu {{.*}},zero,[[T3]]
+
 define internal i32 @icmpSgt64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp sgt i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpSgt64Bool
 ; CHECK: cmp
 ; CHECK: jg
 ; CHECK: jl
 ; CHECK: cmp
 ; CHECK: ja
 ;
 ; OPTM1-LABEL: icmpSgt64Bool
 ; OPTM1: cmp
 ; OPTM1: jg
 ; OPTM1: jl
 ; OPTM1: cmp
 ; OPTM1: ja
 
 ; ARM32-LABEL: icmpSgt64Bool
 ; ARM32: mov
 ; ARM32: cmp
 ; ARM32: sbcs
 ; ARM32: movlt
 
+; MIPS32-LABEL: icmpSgt64Bool
+; MIPS32: xor   [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32: slt   [[T2:.*]],{{.*}},{{.*}}
+; MIPS32: sltu  [[T3:.*]],{{.*}},{{.*}}
+; MIPS32: movz  [[T2]],[[T3]],[[T1]]
+; MIPS32-O2: move       {{.*}},[[T2]]

[Jim Stichnoth, 2016/09/27 13:45:35]

The "MIPS32-O2" and "MIPS32-OM1" lines don't actually do anything because MIPS32
is only being tested with "--check-prefix MIPS32".

It would be great if you could add change this file so that both O2 and Om1 are
being tested, but it's possible that could end up being too big for this CL.

Otherwise, the simplest may be to add "--check-prefix MIPS32-O2" to the RUN
command and handle MIPS32-OM1 later.

[sagar.thakur, 2016/09/28 08:23:23]

Done. I will add RUN command line for Om1 in a separate CL.

+; MIPS32-OM1: sw        [[T2]],[[MEM:.*]]
+; MIPS32-OM1: lb        {{.*}},[[MEM]]
+
 define internal i32 @icmpUgt64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp ugt i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpUgt64Bool
 ; CHECK: cmp
 ; CHECK: ja
 ; CHECK: jb
 ; CHECK: cmp
 ; CHECK: ja
 ;
 ; OPTM1-LABEL: icmpUgt64Bool
 ; OPTM1: cmp
 ; OPTM1: ja
 ; OPTM1: jb
 ; OPTM1: cmp
 ; OPTM1: ja
 
 ; ARM32-LABEL: icmpUgt64Bool
 ; ARM32: mov
 ; ARM32: cmp
 ; ARM32: cmpeq
 ; ARM32: movhi
 
+; MIPS32-LABEL: icmpUgt64Bool
+; MIPS32: xor   [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32: sltu  [[T2:.*]],[[B_HI]],[[A_HI]]
+; MIPS32: sltu  [[T3:.*]],{{.*}},{{.*}}
+; MIPS32: movz  [[T2]],[[T3]],[[T1]]
+; MIPS32-O2: move       {{.*}},[[T2]]
+; MIPS32-OM1: sw        [[T2]],[[MEM:.*]]
+; MIPS32-OM1: lb        {{.*}},[[MEM]]
+
 define internal i32 @icmpSge64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp sge i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpSge64Bool
 ; CHECK: cmp
 ; CHECK: jg
 ; CHECK: jl
 ; CHECK: cmp
 ; CHECK: jae
 ;
 ; OPTM1-LABEL: icmpSge64Bool
 ; OPTM1: cmp
 ; OPTM1: jg
 ; OPTM1: jl
 ; OPTM1: cmp
 ; OPTM1: jae
 
 ; ARM32-LABEL: icmpSge64Bool
 ; ARM32: mov
 ; ARM32: cmp
 ; ARM32: sbcs
 ; ARM32: movge
 
+; MIPS32-LABEL: icmpSge64Bool
+; MIPS32: xor   [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32: slt   [[T2:.*]],[[A_HI]],[[B_HI]]
+; MIPS32: xori  [[T3:.*]],[[T2]],0x1
+; MIPS32: sltu  [[T4:.*]],{{.*}},{{.*}}
+; MIPS32: xori  [[T5:.*]],[[T4]],0x1
+; MIPS32: movz  [[T6:.*]],[[T5]],[[T1]]
+; MIPS32-O2: move       {{.*}},[[T3]]
+; MIPS32-OM1: sw        [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb        {{.*}},[[MEM]]
+
 define internal i32 @icmpUge64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp uge i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpUge64Bool
 ; CHECK: cmp
 ; CHECK: ja
 ; CHECK: jb
 ; CHECK: cmp
 ; CHECK: jae
 ;
 ; OPTM1-LABEL: icmpUge64Bool
 ; OPTM1: cmp
 ; OPTM1: ja
 ; OPTM1: jb
 ; OPTM1: cmp
 ; OPTM1: jae
 
 ; ARM32-LABEL: icmpUge64Bool
 ; ARM32: mov
 ; ARM32: cmp
 ; ARM32: cmpeq
 ; ARM32: movcs
 
+; MIPS32-LABEL: icmpUge64Bool
+; MIPS32: xor   [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32: sltu  [[T2:.*]],[[A_HI]],[[B_HI]]
+; MIPS32: xori  [[T3:.*]],[[T2]],0x1
+; MIPS32: sltu  [[T4:.*]],{{.*}},{{.*}}
+; MIPS32: xori  [[T5:.*]],[[T4]],0x1
+; MIPS32: movz  [[T6:.*]],[[T5]],[[T1]]
+; MIPS32-O2: move       {{.*}},[[T3]]
+; MIPS32-OM1: sw        [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb        {{.*}},[[MEM]]
+
 define internal i32 @icmpSlt64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp slt i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpSlt64Bool
 ; CHECK: cmp
 ; CHECK: jl
 ; CHECK: jg
 ; CHECK: cmp
 ; CHECK: jb
 ;
 ; OPTM1-LABEL: icmpSlt64Bool
 ; OPTM1: cmp
 ; OPTM1: jl
 ; OPTM1: jg
 ; OPTM1: cmp
 ; OPTM1: jb
 
 ; ARM32-LABEL: icmpSlt64Bool
 ; ARM32: mov
 ; ARM32: cmp
 ; ARM32: sbcs
 ; ARM32: movlt
 
+; MIPS32-LABEL: icmpSlt64Bool
+; MIPS32: xor   [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32: slt   [[T2:.*]],[[A_HI]],[[B_HI]]
+; MIPS32: sltu  [[T3:.*]],{{.*}},{{.*}}
+; MIPS32: movz  [[T2:.*]],[[T3]],[[T1]]
+; MIPS32-O2: move       {{.*}},[[T2]]
+; MIPS32-OM1: sw        [[T2]],[[MEM:.*]]
+; MIPS32-OM1: lb        {{.*}},[[MEM]]
+
 define internal i32 @icmpUlt64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp ult i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpUlt64Bool
 ; CHECK: cmp
 ; CHECK: jb
 ; CHECK: ja
 ; CHECK: cmp
 ; CHECK: jb
 ;
 ; OPTM1-LABEL: icmpUlt64Bool
 ; OPTM1: cmp
 ; OPTM1: jb
 ; OPTM1: ja
 ; OPTM1: cmp
 ; OPTM1: jb
 
 ; ARM32-LABEL: icmpUlt64Bool
 ; ARM32: mov
 ; ARM32: cmp
 ; ARM32: cmpeq
 ; ARM32: movcc
 
+; MIPS32-LABEL: icmpUlt64Bool
+; MIPS32: xor   [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32: sltu  [[T2:.*]],[[A_HI]],[[B_HI]]
+; MIPS32: sltu  [[T3:.*]],{{.*}},{{.*}}
+; MIPS32: movz  [[T2:.*]],[[T3]],[[T1]]
+; MIPS32-O2: move       {{.*}},[[T2]]
+; MIPS32-OM1: sw        [[T2]],[[MEM:.*]]
+; MIPS32-OM1: lb        {{.*}},[[MEM]]
+
 define internal i32 @icmpSle64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp sle i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpSle64Bool
 ; CHECK: cmp
 ; CHECK: jl
 ; CHECK: jg
 ; CHECK: cmp
 ; CHECK: jbe
 ;
 ; OPTM1-LABEL: icmpSle64Bool
 ; OPTM1: cmp
 ; OPTM1: jl
 ; OPTM1: jg
 ; OPTM1: cmp
 ; OPTM1: jbe
 
 ; ARM32-LABEL: icmpSle64Bool
 ; ARM32: mov
 ; ARM32: cmp
 ; ARM32: sbcs
 ; ARM32: movge
 
+; MIPS32-LABEL: icmpSle64Bool
+; MIPS32: xor   [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32: slt   [[T2:.*]],[[B_HI]],[[A_HI]]
+; MIPS32: xori  [[T3:.*]],[[T2]],0x1
+; MIPS32: sltu  [[T4:.*]],{{.*}},{{.*}}
+; MIPS32: xori  [[T5:.*]],[[T4]],0x1
+; MIPS32: movz  [[T6:.*]],[[T5]],[[T1]]
+; MIPS32-O2: move       {{.*}},[[T3]]
+; MIPS32-OM1: sw        [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb        {{.*}},[[MEM]]
+
 define internal i32 @icmpUle64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp ule i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpUle64Bool
 ; CHECK: cmp
 ; CHECK: jb
 ; CHECK: ja
 ; CHECK: cmp
 ; CHECK: jbe
 ;
 ; OPTM1-LABEL: icmpUle64Bool
 ; OPTM1: cmp
 ; OPTM1: jb
 ; OPTM1: ja
 ; OPTM1: cmp
 ; OPTM1: jbe
 
 ; ARM32-LABEL: icmpUle64Bool
 ; ARM32: mov
 ; ARM32: cmp
 ; ARM32: cmpeq
 ; ARM32: movls
 
+; MIPS32-LABEL: icmpUle64Bool
+; MIPS32: xor   [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
+; MIPS32: sltu  [[T2:.*]],[[B_HI]],[[A_HI]]
+; MIPS32: xori  [[T3:.*]],[[T2]],0x1
+; MIPS32: sltu  [[T4:.*]],{{.*}},{{.*}}
+; MIPS32: xori  [[T5:.*]],[[T4]],0x1
+; MIPS32: movz  [[T6:.*]],[[T5]],[[T1]]
+; MIPS32-O2: move       {{.*}},[[T3]]
+; MIPS32-OM1: sw        [[T3]],[[MEM:.*]]
+; MIPS32-OM1: lb        {{.*}},[[MEM]]
+
 define internal i64 @load64(i32 %a) {
 entry:
   %__1 = inttoptr i32 %a to i64*
   %v0 = load i64, i64* %__1, align 1
   ret i64 %v0
 }
 ; CHECK-LABEL: load64
 ; CHECK: mov e[[REGISTER:[a-z]+]],DWORD PTR [esp+0x4]
 ; CHECK-NEXT: mov {{.*}},DWORD PTR [e[[REGISTER]]]
 ; CHECK-NEXT: mov {{.*}},DWORD PTR [e[[REGISTER]]+0x4]
@@ skipping 294 matching lines @@
   %s = lshr i64 %a, 40
   %t = trunc i64 %s to i32
   %r = sub i32 %t, 1
   ret i32 %r
 ; ARM32-LABEL: subOneToUpperAfterShift
 ; ARM32: subs
 ; ARM32: sbc
 ; ARM32: lsr
 ; ARM32: sub
 }