ARM EH: Extend DWARF_FRAME_REGISTERS count to 48 and map reg# 256 -> 16.

gcc/unwind-pnacl.h

Index: gcc/unwind-pnacl.h
diff --git a/gcc/unwind-pnacl.h b/gcc/unwind-pnacl.h
index cd5e839f4db9b6e0474c0c03ece19bc60a402fd7..1d5ff86d6fc09d9f6798e9dbd510d80dc1292dc3 100644
--- a/gcc/unwind-pnacl.h
+++ b/gcc/unwind-pnacl.h
@@ -24,7 +24,12 @@
 #if defined(__x86_64__) || defined(__i386__)
 #define DWARF_FRAME_REGISTERS 17
 #elif defined(__arm__)
-#define DWARF_FRAME_REGISTERS 16
+/*
+ * r0-15, and map 256-287 for d0-d31 into regno 16 -> 48.
+ * See:
+ *http://infocenter.arm.com/help/topic/com.arm.doc.ihi0040b/IHI0040B_aadwarf.pdf
+ */
+#define DWARF_FRAME_REGISTERS 48
 #elif defined(__mips__)
 /*
  * Number of hardware registers we use in PNaCl. We have:
@@ -61,11 +66,14 @@
    definition of __builtin_init_dwarf_reg_size_table().  */
 
 #elif defined(__arm__)
-/* All regs are 32bit = 4 bytes */
-#define __builtin_init_dwarf_reg_size_table(table) do { \
-  int i; \
-  for (i = 0; i < DWARF_FRAME_REGISTERS; ++i) \
-    table[i] = 4; \
+#define __builtin_init_dwarf_reg_size_table(table) do {                 \
+  int i;                                                                \
+  /* Integer registers are 32bit. */                                    \
+  for (i = 0; i < 16; ++i)                                              \
+    table[i] = 4;                                                       \
+  /* The rest are VFPv3/NEON (64bit). */                                \
+  for (i = 16; i < DWARF_FRAME_REGISTERS; ++i)                          \
+    table[i] = 8;                                                       \
 } while (0)
 
 #elif defined(__mips__)
@@ -107,4 +115,3 @@
 #endif
 
 #endif /* UNWIND_PNACL_H */
-