src/IceInstMIPS32.h - Issue 2359713003: [Subzero][MIPS32] Implements 64-bit shl, lshr, ashr for MIPS

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Unified Diff: src/IceInstMIPS32.h

Issue 2359713003: [Subzero][MIPS32] Implements 64-bit shl, lshr, ashr for MIPS (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master

Patch Set: Added lowering of shifts operations with constant shift amount Created 4 years, 3 months ago

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Index: src/IceInstMIPS32.h

diff --git a/src/IceInstMIPS32.h b/src/IceInstMIPS32.h

index a4660592747bed11cde48086a3f3338e1c19dbcf..887c6aff7191c32f063a6898c02133b56b7a2f79 100644

--- a/src/IceInstMIPS32.h

+++ b/src/IceInstMIPS32.h

@@ -1003,7 +1003,7 @@ public:

if (!BuildDefs::dump())

return;

Ostream &Str = Func->getContext()->getStrEmit();

- assert(getSrcSize() == 2);

+ assert(getSrcSize() == 3);

Str << "\t" << Opcode << "\t";

getDest()->emit(Func);

Str << ", ";

@@ -1035,6 +1035,7 @@ private:

: InstMIPS32(Func, K, 2, Dest) {

addSource(Src);

addSource(FCC);

+ addSource(Dest);

Jim Stichnoth 2016/09/23 18:49:11 I think this change should be reverted - it should

}

static const char *Opcode;

@@ -1084,7 +1085,7 @@ using InstMIPS32Mflo = InstMIPS32UnaryopGPR<InstMIPS32::Mflo>;

using InstMIPS32Mov_d = InstMIPS32TwoAddrFPR<InstMIPS32::Mov_d>;

using InstMIPS32Mov_s = InstMIPS32TwoAddrFPR<InstMIPS32::Mov_s>;

using InstMIPS32Movf = InstMIPS32MovConditional<InstMIPS32::Movf>;

-using InstMIPS32Movn = InstMIPS32ThreeAddrGPR<InstMIPS32::Movn>;

+using InstMIPS32Movn = InstMIPS32MovConditional<InstMIPS32::Movn>;

using InstMIPS32Movn_d = InstMIPS32ThreeAddrGPR<InstMIPS32::Movn_d>;

using InstMIPS32Movn_s = InstMIPS32ThreeAddrGPR<InstMIPS32::Movn_s>;

using InstMIPS32Movt = InstMIPS32MovConditional<InstMIPS32::Movt>;

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