Subzero, MIPS32: Floating point support in ELF output

src/IceAssemblerMIPS32.h

Index: src/IceAssemblerMIPS32.h
diff --git a/src/IceAssemblerMIPS32.h b/src/IceAssemblerMIPS32.h
index eefb1b2004e7f0e55c73013bba50967dd4b17d15..32a50b6f8a578af0a121f48cc09d37ca1ea8d57f 100644
--- a/src/IceAssemblerMIPS32.h
+++ b/src/IceAssemblerMIPS32.h
@@ -27,6 +27,13 @@ namespace MIPS32 {
 using IValueT = uint32_t;
 using IOffsetT = int32_t;
 
+enum FPInstDataFormat {
+  SinglePrecision = 16,
+  DoublePrecision = 17,
+  Word = 20,
+  Long = 21
+};
+
 class AssemblerMIPS32 : public Assembler {
   AssemblerMIPS32(const AssemblerMIPS32 &) = delete;
   AssemblerMIPS32 &operator=(const AssemblerMIPS32 &) = delete;
@@ -54,17 +61,75 @@ public:
   void nop();
 
   void emitRtRsImm16(IValueT Opcode, const Operand *OpRt, const Operand *OpRs,
-                     const uint32_t Imm, const char *InsnName);
+                     uint32_t Imm, const char *InsnName);
+
+  void emitFtRsImm16(IValueT Opcode, const Operand *OpFt, const Operand *OpRs,
+                     uint32_t Imm, const char *InsnName);
 
   void emitRdRtSa(IValueT Opcode, const Operand *OpRd, const Operand *OpRt,
-                  const uint32_t Sa, const char *InsnName);
+                  uint32_t Sa, const char *InsnName);
 
   void emitRdRsRt(IValueT Opcode, const Operand *OpRd, const Operand *OpRs,
                   const Operand *OpRt, const char *InsnName);
 
+  void emitCOP1FmtFsFd(IValueT Opcode, FPInstDataFormat Format,
+                       const Operand *OpFd, const Operand *OpFs,
+                       const char *InsnName);
+
+  void emitCOP1FmtFtFsFd(IValueT Opcode, FPInstDataFormat Format,
+                         const Operand *OpFd, const Operand *OpFs,
+                         const Operand *OpFt, const char *InsnName);
+
+  void emitCOP1FmtRtFsFd(IValueT Opcode, FPInstDataFormat Format,
+                         const Operand *OpFd, const Operand *OpFs,
+                         const Operand *OpRt, const char *InsnName);
+
+  void emitCOP1MovRtFs(IValueT Opcode, const Operand *OpRt, const Operand *OpFs,
+                       const char *InsnName);
+
   void emitBr(const CondMIPS32::Cond Cond, const Operand *OpRs,
               const Operand *OpRt, IOffsetT Offset);
 
+  void abs_d(const Operand *OpFd, const Operand *OpFs);
+
+  void abs_s(const Operand *OpFd, const Operand *OpFs);
+
+  void add_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void add_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void div_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void div_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void mfc1(const Operand *OpRt, const Operand *OpFs);
+
+  void mov_d(const Operand *OpFd, const Operand *OpFs);
+
+  void mov_s(const Operand *OpFd, const Operand *OpFs);
+
+  void movn_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void movn_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void movz_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void movz_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void mtc1(const Operand *OpRt, const Operand *OpFs);
+
+  void mul_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void mul_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void sqrt_d(const Operand *OpFd, const Operand *OpFs);
+
+  void sqrt_s(const Operand *OpFd, const Operand *OpFs);
+
+  void sub_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void sub_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
   void addiu(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
 
   void slti(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);