Subzero, MIPS32: Floating point support in ELF output

src/IceAssemblerMIPS32.h

 //===- subzero/src/IceAssemblerMIPS32.h - Assembler for MIPS ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Declares the Assembler class for MIPS32.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICEASSEMBLERMIPS32_H
 #define SUBZERO_SRC_ICEASSEMBLERMIPS32_H
 
 #include "IceAssembler.h"
 #include "IceDefs.h"
 #include "IceFixups.h"
 #include "IceInstMIPS32.h"
 #include "IceTargetLowering.h"
 
 namespace Ice {
 namespace MIPS32 {
 
 using IValueT = uint32_t;
 using IOffsetT = int32_t;
 
+enum FPInstDataFormat {
+  SinglePrecision = 16,
+  DoublePrecision = 17,
+  Word = 20,
+  Long = 21
+};
+
 class AssemblerMIPS32 : public Assembler {
   AssemblerMIPS32(const AssemblerMIPS32 &) = delete;
   AssemblerMIPS32 &operator=(const AssemblerMIPS32 &) = delete;
 
 public:
   explicit AssemblerMIPS32(bool use_far_branches = false)
       : Assembler(Asm_MIPS32) {
     // This mode is only needed and implemented for MIPS32 and ARM.
     assert(!use_far_branches);
     (void)use_far_branches;
   }
   ~AssemblerMIPS32() override {
     if (BuildDefs::asserts()) {
       for (const Label *Label : CfgNodeLabels) {
         Label->finalCheck();
       }
       for (const Label *Label : LocalLabels) {
         Label->finalCheck();
       }
     }
   }
 
   void trap();
 
   void nop();
 
   void emitRtRsImm16(IValueT Opcode, const Operand *OpRt, const Operand *OpRs,
-                     const uint32_t Imm, const char *InsnName);
+                     uint32_t Imm, const char *InsnName);
+
+  void emitFtRsImm16(IValueT Opcode, const Operand *OpFt, const Operand *OpRs,
+                     uint32_t Imm, const char *InsnName);
 
   void emitRdRtSa(IValueT Opcode, const Operand *OpRd, const Operand *OpRt,
-                  const uint32_t Sa, const char *InsnName);
+                  uint32_t Sa, const char *InsnName);
 
   void emitRdRsRt(IValueT Opcode, const Operand *OpRd, const Operand *OpRs,
                   const Operand *OpRt, const char *InsnName);
 
+  void emitCOP1FmtFsFd(IValueT Opcode, FPInstDataFormat Format,
+                       const Operand *OpFd, const Operand *OpFs,
+                       const char *InsnName);
+
+  void emitCOP1FmtFtFsFd(IValueT Opcode, FPInstDataFormat Format,
+                         const Operand *OpFd, const Operand *OpFs,
+                         const Operand *OpFt, const char *InsnName);
+
+  void emitCOP1FmtRtFsFd(IValueT Opcode, FPInstDataFormat Format,
+                         const Operand *OpFd, const Operand *OpFs,
+                         const Operand *OpRt, const char *InsnName);
+
+  void emitCOP1MovRtFs(IValueT Opcode, const Operand *OpRt, const Operand *OpFs,
+                       const char *InsnName);
+
   void emitBr(const CondMIPS32::Cond Cond, const Operand *OpRs,
               const Operand *OpRt, IOffsetT Offset);
 
+  void abs_d(const Operand *OpFd, const Operand *OpFs);
+
+  void abs_s(const Operand *OpFd, const Operand *OpFs);
+
+  void add_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void add_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void div_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void div_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void mfc1(const Operand *OpRt, const Operand *OpFs);
+
+  void mov_d(const Operand *OpFd, const Operand *OpFs);
+
+  void mov_s(const Operand *OpFd, const Operand *OpFs);
+
+  void movn_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void movn_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void movz_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void movz_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void mtc1(const Operand *OpRt, const Operand *OpFs);
+
+  void mul_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void mul_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void sqrt_d(const Operand *OpFd, const Operand *OpFs);
+
+  void sqrt_s(const Operand *OpFd, const Operand *OpFs);
+
+  void sub_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
+  void sub_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
+
   void addiu(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
 
   void slti(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
 
   void sltiu(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
 
   void and_(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
 
   void andi(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
 
@@ skipping 95 matching lines @@
   void emitInst(IValueT Value) {
     AssemblerBuffer::EnsureCapacity _(&Buffer);
     Buffer.emit<IValueT>(Value);
   }
 };
 
 } // end of namespace MIPS32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERMIPS32_H