Revert of [x64] Zero/sign-extend loads to 64-bit registers.

src/compiler/x64/instruction-selector-x64.cc

Index: src/compiler/x64/instruction-selector-x64.cc
diff --git a/src/compiler/x64/instruction-selector-x64.cc b/src/compiler/x64/instruction-selector-x64.cc
index 167c950d4cff63a9301918ebc961ee378c244f85..7315b22beab771571284b2acd99454ec56eb32ca 100644
--- a/src/compiler/x64/instruction-selector-x64.cc
+++ b/src/compiler/x64/instruction-selector-x64.cc
@@ -1112,36 +1112,7 @@
 
 void InstructionSelector::VisitChangeInt32ToInt64(Node* node) {
   X64OperandGenerator g(this);
-  Node* const value = node->InputAt(0);
-  if (value->opcode() == IrOpcode::kLoad && CanCover(node, value)) {
-    LoadRepresentation load_rep = LoadRepresentationOf(value->op());
-    MachineRepresentation rep = load_rep.representation();
-    InstructionCode opcode = kArchNop;
-    switch (rep) {
-      case MachineRepresentation::kBit:  // Fall through.
-      case MachineRepresentation::kWord8:
-        opcode = load_rep.IsSigned() ? kX64Movsxbq : kX64Movzxbq;
-        break;
-      case MachineRepresentation::kWord16:
-        opcode = load_rep.IsSigned() ? kX64Movsxwq : kX64Movzxwq;
-        break;
-      case MachineRepresentation::kWord32:
-        opcode = kX64Movsxlq;
-        break;
-      default:
-        UNREACHABLE();
-        return;
-    }
-    InstructionOperand outputs[] = {g.DefineAsRegister(node)};
-    size_t input_count = 0;
-    InstructionOperand inputs[3];
-    AddressingMode mode = g.GetEffectiveAddressMemoryOperand(
-        node->InputAt(0), inputs, &input_count);
-    opcode |= AddressingModeField::encode(mode);
-    Emit(opcode, 1, outputs, input_count, inputs);
-  } else {
-    Emit(kX64Movsxlq, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
-  }
+  Emit(kX64Movsxlq, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
 }