[stubs,interpreter] Optimise SMI loading for 64-bit targets.

[stubs,interpreter] Optimise SMI loading for 64-bit targets.

Adding new methods to the code stub assembler and interpreter
assembler to combine loading and untagging SMIs, so that on 64-bit
architectures we can avoid loading the full 64 bits and load the
32 interesting bits directly instead.

Committed: https://crrev.com/28e3467a72755b05ff5f6c9996955f5eb10e3971
Cr-Commit-Position: refs/heads/master@{#38361}

[georgia.kouveli, 2016-07-27 12:53:19]

georgia.kouveli@arm.com changed reviewers:
+ bmeurer@chromium.org, epertoso@chromium.org

[Benedikt Meurer, 2016-07-28 16:40:48]

Hey Georgia,

Thanks for the CL, but I think this is a bit redundant w/ what
SimplifiedLowering does now. Do you still see this in the wild?

-- Benedikt

[georgia.kouveli, 2016-07-28 16:53:12]

Hi Benedikt,

Yes, we hit the pattern in a couple of stubs and in a few interpreter bytecodes
(the Jump*Constant ones) - those don't go through SimplifiedLowering as far as I
can tell.

[Benedikt Meurer, 2016-07-29 03:31:52]

No, those go directly to the instruction selection. But in that case we might be
able to fix it on the CodeStubAssembler level, i.e. do special casing for 64-bit
architectures with 32-bit Smis, so we have this on all platforms (and it's
probably easier there).

[georgia.kouveli, 2016-08-04 16:54:09]

Description was changed from

==========
[arm64] Optimise SMI loading.

Instead of loading 64 bits and shifting:

  ldr x0, [x1, #offset]
  asr x0, x0, #32

directly load the interesting 32 bits and sign-extend:

  ldrsw x0, [x1, #offset+4]

Similarly, optimize:

  add x2, x2, #offset
  ldr x0, [x1, x2]
  asr x0, x0, #32

to:

  add x2, x2, #offset+4
  ldrsw x0, [x1, x2]

BUG=
==========

to

==========
[stubs,interpreter] Optimise SMI loading for 64-bit targets.
    
Adding new methods to the code stub assembler and interpreter
assembler to combine loading and untagging SMIs, so that on 64-bit
architectures we can avoid loading the full 64 bits and load the
32 interesting bits directly instead.
==========

[georgia.kouveli, 2016-08-04 16:59:37]

PTAL! I've modified the stubs and interpreter bytecodes where we hit this
pattern so that we special-case this for 64-bit architectures and generate a
32-bit load instead. I've updated ARM64 to recognise the load + sign-extend
pattern, it might be the case that other backends also need to do something
similar.

[Benedikt Meurer, 2016-08-05 04:31:40]

Nice, thanks. LGTM.

Enrico: Can you port the instruction selector magic to x64?

[georgia.kouveli, 2016-08-05 09:11:33]

The CQ bit was checked by georgia.kouveli@arm.com

[commit-bot: I haz the power, 2016-08-05 09:11:36]

CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2016-08-05 09:33:14]

Description was changed from

==========
[stubs,interpreter] Optimise SMI loading for 64-bit targets.
    
Adding new methods to the code stub assembler and interpreter
assembler to combine loading and untagging SMIs, so that on 64-bit
architectures we can avoid loading the full 64 bits and load the
32 interesting bits directly instead.
==========

to

==========
[stubs,interpreter] Optimise SMI loading for 64-bit targets.
    
Adding new methods to the code stub assembler and interpreter
assembler to combine loading and untagging SMIs, so that on 64-bit
architectures we can avoid loading the full 64 bits and load the
32 interesting bits directly instead.
==========

[commit-bot: I haz the power, 2016-08-05 09:33:15]

Committed patchset #2 (id:20001)

[commit-bot: I haz the power, 2016-08-05 09:34:19]

Description was changed from

==========
[stubs,interpreter] Optimise SMI loading for 64-bit targets.
    
Adding new methods to the code stub assembler and interpreter
assembler to combine loading and untagging SMIs, so that on 64-bit
architectures we can avoid loading the full 64 bits and load the
32 interesting bits directly instead.
==========

to

==========
[stubs,interpreter] Optimise SMI loading for 64-bit targets.

Adding new methods to the code stub assembler and interpreter
assembler to combine loading and untagging SMIs, so that on 64-bit
architectures we can avoid loading the full 64 bits and load the
32 interesting bits directly instead.

Committed: https://crrev.com/28e3467a72755b05ff5f6c9996955f5eb10e3971
Cr-Commit-Position: refs/heads/master@{#38361}
==========

[commit-bot: I haz the power, 2016-08-05 09:34:20]

Patchset 2 (id:??) landed as
https://crrev.com/28e3467a72755b05ff5f6c9996955f5eb10e3971
Cr-Commit-Position: refs/heads/master@{#38361}