Reorder X8664 Register Defs so that scratch registers are allocated first

Reorder X8664 Register Defs so that scratch registers are allocated first

Reduces register pressure and the number of push/pops slightly.

BUG=none
R=stichnot@chromium.org

Committed: https://gerrit.chromium.org/gerrit/gitweb?p=native_client/pnacl-subzero.git;a=commit;h=fe2caab8cb0fecc764fdb710014b3a60b9d7b2d2

[manasijm, 2016-06-27 21:21:44]

manasijm@google.com changed reviewers:
+ eholk@chromium.org, jpp@chromium.org, kschimpf@google.com,
stichnot@chromium.org

[Jim Stichnoth, 2016-06-27 22:06:55]

https://codereview.chromium.org/2100333002/diff/1/src/IceInstX8664.cpp
File src/IceInstX8664.cpp (left):

https://codereview.chromium.org/2100333002/diff/1/src/IceInstX8664.cpp#oldcod...
src/IceInstX8664.cpp:166: assert(Base->getRegNum() == RegX8664::Encoded_Reg_rsp
||
This assert can/should stay.

However, change "Base->getRegNum()" to "getEncodedGPR(Base->getRegNum())".

https://codereview.chromium.org/2100333002/diff/1/src/IceInstX8664.cpp
File src/IceInstX8664.cpp (right):

https://codereview.chromium.org/2100333002/diff/1/src/IceInstX8664.cpp#newcod...
src/IceInstX8664.cpp:164: // For filetype=asm, they need to be emitted as their
32-bit sibilings.
siblings

https://codereview.chromium.org/2100333002/diff/1/src/IceInstX8664.def
File src/IceInstX8664.def (right):

https://codereview.chromium.org/2100333002/diff/1/src/IceInstX8664.def#newcode24
src/IceInstX8664.def:24: //                 xmm8, xmm9, xmm10, xmm11, xmm12,
xmm13, xmm14, xmm15
Here it would be good to add a comment that the scratch registers are listed
first, followed by preserved registers, so that the register allocator will
favor scratch registers.

https://codereview.chromium.org/2100333002/diff/1/src/IceInstX8664.def#newcode69
src/IceInstX8664.def:69: X(Reg_spl,   4, "spl",  Reg_rsp, 0,0,1,0,0, 1,0,0,0,0,
0, 0,0,0,0,0,         \
Can you arrange the encoding order to be 3/4/5 instead of 4/3/5?

[manasijm, 2016-06-27 22:37:09]

https://codereview.chromium.org/2100333002/diff/1/src/IceInstX8664.cpp
File src/IceInstX8664.cpp (left):

https://codereview.chromium.org/2100333002/diff/1/src/IceInstX8664.cpp#oldcod...
src/IceInstX8664.cpp:166: assert(Base->getRegNum() == RegX8664::Encoded_Reg_rsp
||
On 2016/06/27 22:06:55, stichnot wrote:
> This assert can/should stay.
> 
> However, change "Base->getRegNum()" to "getEncodedGPR(Base->getRegNum())".

Done.

https://codereview.chromium.org/2100333002/diff/1/src/IceInstX8664.cpp
File src/IceInstX8664.cpp (right):

https://codereview.chromium.org/2100333002/diff/1/src/IceInstX8664.cpp#newcod...
src/IceInstX8664.cpp:164: // For filetype=asm, they need to be emitted as their
32-bit sibilings.
On 2016/06/27 22:06:55, stichnot wrote:
> siblings

Done.

https://codereview.chromium.org/2100333002/diff/1/src/IceInstX8664.def
File src/IceInstX8664.def (right):

https://codereview.chromium.org/2100333002/diff/1/src/IceInstX8664.def#newcode69
src/IceInstX8664.def:69: X(Reg_spl,   4, "spl",  Reg_rsp, 0,0,1,0,0, 1,0,0,0,0,
0, 0,0,0,0,0,         \
On 2016/06/27 22:06:55, stichnot wrote:
> Can you arrange the encoding order to be 3/4/5 instead of 4/3/5?

Done.

[Jim Stichnoth, 2016-06-27 22:38:43]

lgtm

[manasijm, 2016-06-27 22:42:15]

Description was changed from

==========
Reorder X8664 Register Defs so that scratch registers are allocated first

Reduces register pressure and the number of push/pops slightly.

BUG=none
==========

to

==========
Reorder X8664 Register Defs so that scratch registers are allocated first

Reduces register pressure and the number of push/pops slightly.

BUG=none
R=stichnot@chromium.org

Committed:
https://gerrit.chromium.org/gerrit/gitweb?p=native_client/pnacl-subzero.git;a...
==========

[manasijm, 2016-06-27 22:42:17]

Committed patchset #2 (id:20001) manually as
fe2caab8cb0fecc764fdb710014b3a60b9d7b2d2 (presubmit successful).