[RegisterConfiguration] Streamline access to arch defaults, simplify Registers.

src/compiler/instruction.cc

Index: src/compiler/instruction.cc
diff --git a/src/compiler/instruction.cc b/src/compiler/instruction.cc
index d3459284955e2b99d3753cfd99075af52446f740..5ca3600375aafd8f4b7bd5d55a0742235d732702 100644
--- a/src/compiler/instruction.cc
+++ b/src/compiler/instruction.cc
@@ -12,6 +12,7 @@ namespace v8 {
 namespace internal {
 namespace compiler {
 
+const auto GetRegConfig = RegisterConfiguration::Turbofan;
 
 FlagsCondition CommuteFlagsCondition(FlagsCondition condition) {
   switch (condition) {
@@ -64,8 +65,7 @@ bool InstructionOperand::InterferesWith(const InstructionOperand& that) const {
 
   const LocationOperand& loc1 = *LocationOperand::cast(this);
   const LocationOperand& loc2 = LocationOperand::cast(that);
-  const RegisterConfiguration* config =
-      RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN);
+  const RegisterConfiguration* config = GetRegConfig();
   if (config->fp_aliasing_kind() != RegisterConfiguration::COMBINE)
     return loc1.register_code() == loc2.register_code();
 
@@ -81,12 +81,7 @@ void InstructionOperand::Print(const RegisterConfiguration* config) const {
   os << wrapper << std::endl;
 }
 
-
-void InstructionOperand::Print() const {
-  const RegisterConfiguration* config =
-      RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN);
-  Print(config);
-}
+void InstructionOperand::Print() const { Print(GetRegConfig()); }
 
 std::ostream& operator<<(std::ostream& os,
                          const PrintableInstructionOperand& printable) {
@@ -142,12 +137,18 @@ std::ostream& operator<<(std::ostream& os,
       } else if (op.IsFPStackSlot()) {
         os << "[fp_stack:" << allocated.index();
       } else if (op.IsRegister()) {
-        os << "[" << allocated.GetRegister().ToString() << "|R";
+        os << "["
+           << GetRegConfig()->GetGeneralRegisterName(allocated.register_code())
+           << "|R";
       } else if (op.IsDoubleRegister()) {
-        os << "[" << allocated.GetDoubleRegister().ToString() << "|R";
+        os << "["
+           << GetRegConfig()->GetDoubleRegisterName(allocated.register_code())
+           << "|R";
       } else {
         DCHECK(op.IsFloatRegister());
-        os << "[" << allocated.GetFloatRegister().ToString() << "|R";
+        os << "["
+           << GetRegConfig()->GetFloatRegisterName(allocated.register_code())
+           << "|R";
       }
       if (allocated.IsExplicit()) {
         os << "|E";
@@ -203,13 +204,7 @@ void MoveOperands::Print(const RegisterConfiguration* config) const {
   os << wrapper << std::endl;
 }
 
-
-void MoveOperands::Print() const {
-  const RegisterConfiguration* config =
-      RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN);
-  Print(config);
-}
-
+void MoveOperands::Print() const { Print(GetRegConfig()); }
 
 std::ostream& operator<<(std::ostream& os,
                          const PrintableMoveOperands& printable) {
@@ -258,14 +253,11 @@ ExplicitOperand::ExplicitOperand(LocationKind kind, MachineRepresentation rep,
                                  int index)
     : LocationOperand(EXPLICIT, kind, rep, index) {
   DCHECK_IMPLIES(kind == REGISTER && !IsFloatingPoint(rep),
-                 Register::from_code(index).IsAllocatable(
-                     RegisterConfiguration::TURBOFAN));
+                 GetRegConfig()->IsAllocatableGeneralCode(index));
   DCHECK_IMPLIES(kind == REGISTER && rep == MachineRepresentation::kFloat32,
-                 FloatRegister::from_code(index).IsAllocatable(
-                     RegisterConfiguration::TURBOFAN));
+                 GetRegConfig()->IsAllocatableFloatCode(index));
   DCHECK_IMPLIES(kind == REGISTER && (rep == MachineRepresentation::kFloat64),
-                 DoubleRegister::from_code(index).IsAllocatable(
-                     RegisterConfiguration::TURBOFAN));
+                 GetRegConfig()->IsAllocatableDoubleCode(index));
 }
 
 Instruction::Instruction(InstructionCode opcode)
@@ -326,13 +318,7 @@ void Instruction::Print(const RegisterConfiguration* config) const {
   os << wrapper << std::endl;
 }
 
-
-void Instruction::Print() const {
-  const RegisterConfiguration* config =
-      RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN);
-  Print(config);
-}
-
+void Instruction::Print() const { Print(GetRegConfig()); }
 
 std::ostream& operator<<(std::ostream& os,
                          const PrintableParallelMove& printable) {
@@ -360,9 +346,7 @@ void ReferenceMap::RecordReference(const AllocatedOperand& op) {
 std::ostream& operator<<(std::ostream& os, const ReferenceMap& pm) {
   os << "{";
   bool first = true;
-  PrintableInstructionOperand poi = {
-      RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN),
-      InstructionOperand()};
+  PrintableInstructionOperand poi = {GetRegConfig(), InstructionOperand()};
   for (const InstructionOperand& op : pm.reference_operands_) {
     if (!first) {
       os << ";";
@@ -897,12 +881,7 @@ void InstructionSequence::Print(const RegisterConfiguration* config) const {
   os << wrapper << std::endl;
 }
 
-
-void InstructionSequence::Print() const {
-  const RegisterConfiguration* config =
-      RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN);
-  Print(config);
-}
+void InstructionSequence::Print() const { Print(GetRegConfig()); }
 
 void InstructionSequence::PrintBlock(const RegisterConfiguration* config,
                                      int block_id) const {
@@ -956,9 +935,7 @@ void InstructionSequence::PrintBlock(const RegisterConfiguration* config,
 }
 
 void InstructionSequence::PrintBlock(int block_id) const {
-  const RegisterConfiguration* config =
-      RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN);
-  PrintBlock(config, block_id);
+  PrintBlock(GetRegConfig(), block_id);
 }
 
 FrameStateDescriptor::FrameStateDescriptor(