Use more fpu multi-load/store instructions on ARM.

runtime/vm/flow_graph_compiler_arm.cc

Index: runtime/vm/flow_graph_compiler_arm.cc
===================================================================
--- runtime/vm/flow_graph_compiler_arm.cc	(revision 34308)
+++ runtime/vm/flow_graph_compiler_arm.cc	(working copy)
@@ -1613,12 +1613,8 @@
       } else {
         ASSERT(destination.IsQuadStackSlot());
         const intptr_t dest_offset = destination.ToStackSlotOffset();
-        DRegister dsrc0 = EvenDRegisterOf(source.fpu_reg());
-        DRegister dsrc1 = OddDRegisterOf(source.fpu_reg());
-        // TODO(zra): Write and use {Load,Store}Q{From,To}Offset(), which can
-        // use a single vld1/vst1 instruction.
-        __ StoreDToOffset(dsrc0, FP, dest_offset);
-        __ StoreDToOffset(dsrc1, FP, dest_offset + 2*kWordSize);
+        const DRegister dsrc0 = EvenDRegisterOf(source.fpu_reg());
+        __ StoreMultipleDToOffset(dsrc0, 2, FP, dest_offset);
       }
     }
   } else if (source.IsDoubleStackSlot()) {
@@ -1636,20 +1632,15 @@
   } else if (source.IsQuadStackSlot()) {
     if (destination.IsFpuRegister()) {
       const intptr_t dest_offset = source.ToStackSlotOffset();
-      DRegister dst0 = EvenDRegisterOf(destination.fpu_reg());
-      DRegister dst1 = OddDRegisterOf(destination.fpu_reg());
-      __ LoadDFromOffset(dst0, FP, dest_offset);
-      __ LoadDFromOffset(dst1, FP, dest_offset + 2*kWordSize);
+      const DRegister dst0 = EvenDRegisterOf(destination.fpu_reg());
+      __ LoadMultipleDFromOffset(dst0, 2, FP, dest_offset);
     } else {
       ASSERT(destination.IsQuadStackSlot());
       const intptr_t source_offset = source.ToStackSlotOffset();
       const intptr_t dest_offset = destination.ToStackSlotOffset();
-      DRegister dtmp0 = DTMP;
-      DRegister dtmp1 = OddDRegisterOf(QTMP);
-      __ LoadDFromOffset(dtmp0, FP, source_offset);
-      __ LoadDFromOffset(dtmp1, FP, source_offset + 2*kWordSize);
-      __ StoreDToOffset(dtmp0, FP, dest_offset);
-      __ StoreDToOffset(dtmp1, FP, dest_offset + 2*kWordSize);
+      const DRegister dtmp0 = DTMP;
+      __ LoadMultipleDFromOffset(dtmp0, 2, FP, source_offset);
+      __ StoreMultipleDToOffset(dtmp0, 2, FP, dest_offset);
     }
   } else {
     ASSERT(source.IsConstant());