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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. | 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. |
| 6 #if defined(TARGET_ARCH_ARM) | 6 #if defined(TARGET_ARCH_ARM) |
| 7 | 7 |
| 8 #include "vm/flow_graph_compiler.h" | 8 #include "vm/flow_graph_compiler.h" |
| 9 | 9 |
| 10 #include "vm/ast_printer.h" | 10 #include "vm/ast_printer.h" |
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| 1606 if (destination.IsFpuRegister()) { | 1606 if (destination.IsFpuRegister()) { |
| 1607 __ vmovq(destination.fpu_reg(), source.fpu_reg()); | 1607 __ vmovq(destination.fpu_reg(), source.fpu_reg()); |
| 1608 } else { | 1608 } else { |
| 1609 if (destination.IsDoubleStackSlot()) { | 1609 if (destination.IsDoubleStackSlot()) { |
| 1610 const intptr_t dest_offset = destination.ToStackSlotOffset(); | 1610 const intptr_t dest_offset = destination.ToStackSlotOffset(); |
| 1611 DRegister src = EvenDRegisterOf(source.fpu_reg()); | 1611 DRegister src = EvenDRegisterOf(source.fpu_reg()); |
| 1612 __ StoreDToOffset(src, FP, dest_offset); | 1612 __ StoreDToOffset(src, FP, dest_offset); |
| 1613 } else { | 1613 } else { |
| 1614 ASSERT(destination.IsQuadStackSlot()); | 1614 ASSERT(destination.IsQuadStackSlot()); |
| 1615 const intptr_t dest_offset = destination.ToStackSlotOffset(); | 1615 const intptr_t dest_offset = destination.ToStackSlotOffset(); |
| 1616 DRegister dsrc0 = EvenDRegisterOf(source.fpu_reg()); | 1616 const DRegister dsrc0 = EvenDRegisterOf(source.fpu_reg()); |
| 1617 DRegister dsrc1 = OddDRegisterOf(source.fpu_reg()); | 1617 __ StoreMultipleDToOffset(dsrc0, 2, FP, dest_offset); |
| 1618 // TODO(zra): Write and use {Load,Store}Q{From,To}Offset(), which can | |
| 1619 // use a single vld1/vst1 instruction. | |
| 1620 __ StoreDToOffset(dsrc0, FP, dest_offset); | |
| 1621 __ StoreDToOffset(dsrc1, FP, dest_offset + 2*kWordSize); | |
| 1622 } | 1618 } |
| 1623 } | 1619 } |
| 1624 } else if (source.IsDoubleStackSlot()) { | 1620 } else if (source.IsDoubleStackSlot()) { |
| 1625 if (destination.IsFpuRegister()) { | 1621 if (destination.IsFpuRegister()) { |
| 1626 const intptr_t dest_offset = source.ToStackSlotOffset(); | 1622 const intptr_t dest_offset = source.ToStackSlotOffset(); |
| 1627 DRegister dst = EvenDRegisterOf(destination.fpu_reg()); | 1623 DRegister dst = EvenDRegisterOf(destination.fpu_reg()); |
| 1628 __ LoadDFromOffset(dst, FP, dest_offset); | 1624 __ LoadDFromOffset(dst, FP, dest_offset); |
| 1629 } else { | 1625 } else { |
| 1630 ASSERT(destination.IsDoubleStackSlot()); | 1626 ASSERT(destination.IsDoubleStackSlot()); |
| 1631 const intptr_t source_offset = source.ToStackSlotOffset(); | 1627 const intptr_t source_offset = source.ToStackSlotOffset(); |
| 1632 const intptr_t dest_offset = destination.ToStackSlotOffset(); | 1628 const intptr_t dest_offset = destination.ToStackSlotOffset(); |
| 1633 __ LoadDFromOffset(DTMP, FP, source_offset); | 1629 __ LoadDFromOffset(DTMP, FP, source_offset); |
| 1634 __ StoreDToOffset(DTMP, FP, dest_offset); | 1630 __ StoreDToOffset(DTMP, FP, dest_offset); |
| 1635 } | 1631 } |
| 1636 } else if (source.IsQuadStackSlot()) { | 1632 } else if (source.IsQuadStackSlot()) { |
| 1637 if (destination.IsFpuRegister()) { | 1633 if (destination.IsFpuRegister()) { |
| 1638 const intptr_t dest_offset = source.ToStackSlotOffset(); | 1634 const intptr_t dest_offset = source.ToStackSlotOffset(); |
| 1639 DRegister dst0 = EvenDRegisterOf(destination.fpu_reg()); | 1635 const DRegister dst0 = EvenDRegisterOf(destination.fpu_reg()); |
| 1640 DRegister dst1 = OddDRegisterOf(destination.fpu_reg()); | 1636 __ LoadMultipleDFromOffset(dst0, 2, FP, dest_offset); |
| 1641 __ LoadDFromOffset(dst0, FP, dest_offset); | |
| 1642 __ LoadDFromOffset(dst1, FP, dest_offset + 2*kWordSize); | |
| 1643 } else { | 1637 } else { |
| 1644 ASSERT(destination.IsQuadStackSlot()); | 1638 ASSERT(destination.IsQuadStackSlot()); |
| 1645 const intptr_t source_offset = source.ToStackSlotOffset(); | 1639 const intptr_t source_offset = source.ToStackSlotOffset(); |
| 1646 const intptr_t dest_offset = destination.ToStackSlotOffset(); | 1640 const intptr_t dest_offset = destination.ToStackSlotOffset(); |
| 1647 DRegister dtmp0 = DTMP; | 1641 const DRegister dtmp0 = DTMP; |
| 1648 DRegister dtmp1 = OddDRegisterOf(QTMP); | 1642 __ LoadMultipleDFromOffset(dtmp0, 2, FP, source_offset); |
| 1649 __ LoadDFromOffset(dtmp0, FP, source_offset); | 1643 __ StoreMultipleDToOffset(dtmp0, 2, FP, dest_offset); |
| 1650 __ LoadDFromOffset(dtmp1, FP, source_offset + 2*kWordSize); | |
| 1651 __ StoreDToOffset(dtmp0, FP, dest_offset); | |
| 1652 __ StoreDToOffset(dtmp1, FP, dest_offset + 2*kWordSize); | |
| 1653 } | 1644 } |
| 1654 } else { | 1645 } else { |
| 1655 ASSERT(source.IsConstant()); | 1646 ASSERT(source.IsConstant()); |
| 1656 if (destination.IsRegister()) { | 1647 if (destination.IsRegister()) { |
| 1657 const Object& constant = source.constant(); | 1648 const Object& constant = source.constant(); |
| 1658 __ LoadObject(destination.reg(), constant); | 1649 __ LoadObject(destination.reg(), constant); |
| 1659 } else { | 1650 } else { |
| 1660 ASSERT(destination.IsStackSlot()); | 1651 ASSERT(destination.IsStackSlot()); |
| 1661 const intptr_t dest_offset = destination.ToStackSlotOffset(); | 1652 const intptr_t dest_offset = destination.ToStackSlotOffset(); |
| 1662 __ LoadObject(TMP, source.constant()); | 1653 __ LoadObject(TMP, source.constant()); |
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| 1810 DRegister dreg = EvenDRegisterOf(reg); | 1801 DRegister dreg = EvenDRegisterOf(reg); |
| 1811 __ vldrd(dreg, Address(SP, kDoubleSize, Address::PostIndex)); | 1802 __ vldrd(dreg, Address(SP, kDoubleSize, Address::PostIndex)); |
| 1812 } | 1803 } |
| 1813 | 1804 |
| 1814 | 1805 |
| 1815 #undef __ | 1806 #undef __ |
| 1816 | 1807 |
| 1817 } // namespace dart | 1808 } // namespace dart |
| 1818 | 1809 |
| 1819 #endif // defined TARGET_ARCH_ARM | 1810 #endif // defined TARGET_ARCH_ARM |
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