ARM: Fix Q register encoding

test/cctest/test-disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 669 matching lines @@
 
 TEST(Neon) {
   SET_UP();
 
   if (CpuFeatures::IsSupported(NEON)) {
     CpuFeatureScope scope(&assm, NEON);
       COMPARE(vld1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(r1)),
               "f421420f       vld1.8 {d4, d5, d6, d7}, [r1]");
       COMPARE(vst1(Neon16, NeonListOperand(d17, 4), NeonMemOperand(r9)),
               "f449124f       vst1.16 {d17, d18, d19, d20}, [r9]");
+      COMPARE(vmovl(NeonU8, q3, d1),
+              "f3886a11       vmovl.u8 q3, d1");
       COMPARE(vmovl(NeonU8, q4, d2),
-              "f3884a12       vmovl.u8 q4, d2");
+              "f3888a12       vmovl.u8 q4, d2");
   }
 
   VERIFY_RUN();
 }
 
 
 TEST(LoadStore) {
   SET_UP();
 
   COMPARE(ldrb(r0, MemOperand(r1)),
@@ skipping 191 matching lines @@
             "e16dc7ff       strd ip, [sp, #-127]!");
 
     COMPARE(pld(MemOperand(r1, 0)),
             "f5d1f000       pld [r1]");
     COMPARE(pld(MemOperand(r2, 128)),
             "f5d2f080       pld [r2, #+128]");
   }
 
   VERIFY_RUN();
 }