ARM: Fix Q register encoding

test/cctest/test-assembler-arm.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 1248 matching lines @@
     uint32_t dst4;
     uint32_t dst5;
     uint32_t dst6;
     uint32_t dst7;
     uint32_t srcA0;
     uint32_t srcA1;
     uint32_t dstA0;
     uint32_t dstA1;
     uint32_t dstA2;
     uint32_t dstA3;
+    uint32_t dstA4;
+    uint32_t dstA5;
+    uint32_t dstA6;
+    uint32_t dstA7;
   } T;
   T t;
 
   // Create a function that accepts &t, and loads, manipulates, and stores
   // the doubles and floats.
   Assembler assm(isolate, NULL, 0);
 
 
   if (CpuFeatures::IsSupported(NEON)) {
     CpuFeatureScope scope(&assm, NEON);
 
     __ stm(db_w, sp, r4.bit() | lr.bit());
     // Move 32 bytes with neon.
     __ add(r4, r0, Operand(OFFSET_OF(T, src0)));
     __ vld1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(r4));
     __ add(r4, r0, Operand(OFFSET_OF(T, dst0)));
     __ vst1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(r4));
 
     // Expand 8 bytes into 8 words(16 bits).
     __ add(r4, r0, Operand(OFFSET_OF(T, srcA0)));
     __ vld1(Neon8, NeonListOperand(d0), NeonMemOperand(r4));
     __ vmovl(NeonU8, q0, d0);
     __ add(r4, r0, Operand(OFFSET_OF(T, dstA0)));
     __ vst1(Neon8, NeonListOperand(d0, 2), NeonMemOperand(r4));
 
-  __ ldm(ia_w, sp, r4.bit() | pc.bit());
+    // The same expansion, but with different source and destination registers.
+    __ add(r4, r0, Operand(OFFSET_OF(T, srcA0)));
+    __ vld1(Neon8, NeonListOperand(d1), NeonMemOperand(r4));
+    __ vmovl(NeonU8, q1, d1);
+    __ add(r4, r0, Operand(OFFSET_OF(T, dstA4)));
+    __ vst1(Neon8, NeonListOperand(d2, 2), NeonMemOperand(r4));
+
+    __ ldm(ia_w, sp, r4.bit() | pc.bit());
 
     CodeDesc desc;
     assm.GetCode(&desc);
     Object* code = isolate->heap()->CreateCode(
         desc,
         Code::ComputeFlags(Code::STUB),
         Handle<Code>())->ToObjectChecked();
     CHECK(code->IsCode());
 #ifdef DEBUG
     Code::cast(code)->Print();
@@ skipping 14 matching lines @@
     t.dst4 = 0;
     t.dst5 = 0;
     t.dst6 = 0;
     t.dst7 = 0;
     t.srcA0 = 0x41424344;
     t.srcA1 = 0x81828384;
     t.dstA0 = 0;
     t.dstA1 = 0;
     t.dstA2 = 0;
     t.dstA3 = 0;
+    t.dstA4 = 0;
+    t.dstA5 = 0;
+    t.dstA6 = 0;
+    t.dstA7 = 0;
     Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
     USE(dummy);
     CHECK_EQ(0x01020304, t.dst0);
     CHECK_EQ(0x11121314, t.dst1);
     CHECK_EQ(0x21222324, t.dst2);
     CHECK_EQ(0x31323334, t.dst3);
     CHECK_EQ(0x41424344, t.dst4);
     CHECK_EQ(0x51525354, t.dst5);
     CHECK_EQ(0x61626364, t.dst6);
     CHECK_EQ(0x71727374, t.dst7);
     CHECK_EQ(0x00430044, t.dstA0);
     CHECK_EQ(0x00410042, t.dstA1);
     CHECK_EQ(0x00830084, t.dstA2);
     CHECK_EQ(0x00810082, t.dstA3);
+    CHECK_EQ(0x00430044, t.dstA4);
+    CHECK_EQ(0x00410042, t.dstA5);
+    CHECK_EQ(0x00830084, t.dstA6);
+    CHECK_EQ(0x00810082, t.dstA7);
   }
 }
 
 
 TEST(16) {
   // Test the pkh, uxtb, uxtab and uxtb16 instructions.
   CcTest::InitializeVM();
   Isolate* isolate = CcTest::i_isolate();
   HandleScope scope(isolate);
 
@@ skipping 217 matching lines @@
   Handle<Code> code = isolate->factory()->NewCode(desc,
       Code::ComputeFlags(Code::STUB), code_object);
   CHECK(code->IsCode());
   F1 f = FUNCTION_CAST<F1>(code->entry());
   int res = reinterpret_cast<int>(CALL_GENERATED_CODE(f, 21, 0, 0, 0, 0));
   ::printf("f() = %d\n", res);
   CHECK_EQ(42, res);
 }
 
 #undef __