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Issue 207523005: ARM: Fix Q register encoding (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 9 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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1559 } 1559 }
1560 } 1560 }
1561 1561
1562 1562
1563 void Decoder::DecodeSpecialCondition(Instruction* instr) { 1563 void Decoder::DecodeSpecialCondition(Instruction* instr) {
1564 switch (instr->SpecialValue()) { 1564 switch (instr->SpecialValue()) {
1565 case 5: 1565 case 5:
1566 if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) && 1566 if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
1567 (instr->Bit(4) == 1)) { 1567 (instr->Bit(4) == 1)) {
1568 // vmovl signed 1568 // vmovl signed
1569 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); 1569 if ((instr->VdValue() & 1) != 0) Unknown(instr);
1570 int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
1570 int Vm = (instr->Bit(5) << 4) | instr->VmValue(); 1571 int Vm = (instr->Bit(5) << 4) | instr->VmValue();
1571 int imm3 = instr->Bits(21, 19); 1572 int imm3 = instr->Bits(21, 19);
1572 out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_, 1573 out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
1573 "vmovl.s%d q%d, d%d", imm3*8, Vd, Vm); 1574 "vmovl.s%d q%d, d%d", imm3*8, Vd, Vm);
1574 } else { 1575 } else {
1575 Unknown(instr); 1576 Unknown(instr);
1576 } 1577 }
1577 break; 1578 break;
1578 case 7: 1579 case 7:
1579 if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) && 1580 if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
1580 (instr->Bit(4) == 1)) { 1581 (instr->Bit(4) == 1)) {
1581 // vmovl unsigned 1582 // vmovl unsigned
1582 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); 1583 if ((instr->VdValue() & 1) != 0) Unknown(instr);
1584 int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
1583 int Vm = (instr->Bit(5) << 4) | instr->VmValue(); 1585 int Vm = (instr->Bit(5) << 4) | instr->VmValue();
1584 int imm3 = instr->Bits(21, 19); 1586 int imm3 = instr->Bits(21, 19);
1585 out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_, 1587 out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
1586 "vmovl.u%d q%d, d%d", imm3*8, Vd, Vm); 1588 "vmovl.u%d q%d, d%d", imm3*8, Vd, Vm);
1587 } else { 1589 } else {
1588 Unknown(instr); 1590 Unknown(instr);
1589 } 1591 }
1590 break; 1592 break;
1591 case 8: 1593 case 8:
1592 if (instr->Bits(21, 20) == 0) { 1594 if (instr->Bits(21, 20) == 0) {
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1803 v8::internal::PrintF( 1805 v8::internal::PrintF(
1804 f, "%p %08x %s\n", 1806 f, "%p %08x %s\n",
1805 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); 1807 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
1806 } 1808 }
1807 } 1809 }
1808 1810
1809 1811
1810 } // namespace disasm 1812 } // namespace disasm
1811 1813
1812 #endif // V8_TARGET_ARCH_ARM 1814 #endif // V8_TARGET_ARCH_ARM
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