Index: src/mips/assembler-mips.cc |
diff --git a/src/mips/assembler-mips.cc b/src/mips/assembler-mips.cc |
index 0394e4f17e0b19486b1cd4a8f66927060f9ce643..c384329a6d6d51718eb1da7b62322dbf57754611 100644 |
--- a/src/mips/assembler-mips.cc |
+++ b/src/mips/assembler-mips.cc |
@@ -1293,7 +1293,6 @@ void Assembler::b(int16_t offset) { |
void Assembler::bal(int16_t offset) { |
- positions_recorder()->WriteRecordedPositions(); |
bgezal(zero_reg, offset); |
} |
@@ -1306,7 +1305,6 @@ void Assembler::bc(int32_t offset) { |
void Assembler::balc(int32_t offset) { |
DCHECK(IsMipsArchVariant(kMips32r6)); |
- positions_recorder()->WriteRecordedPositions(); |
GenInstrImmediate(BALC, offset, CompactBranchType::COMPACT_BRANCH); |
} |
@@ -1353,7 +1351,6 @@ void Assembler::bgec(Register rs, Register rt, int16_t offset) { |
void Assembler::bgezal(Register rs, int16_t offset) { |
DCHECK(!IsMipsArchVariant(kMips32r6) || rs.is(zero_reg)); |
BlockTrampolinePoolScope block_trampoline_pool(this); |
- positions_recorder()->WriteRecordedPositions(); |
GenInstrImmediate(REGIMM, rs, BGEZAL, offset); |
BlockTrampolinePoolFor(1); // For associated delay slot. |
} |
@@ -1424,7 +1421,6 @@ void Assembler::bltz(Register rs, int16_t offset) { |
void Assembler::bltzal(Register rs, int16_t offset) { |
DCHECK(!IsMipsArchVariant(kMips32r6) || rs.is(zero_reg)); |
BlockTrampolinePoolScope block_trampoline_pool(this); |
- positions_recorder()->WriteRecordedPositions(); |
GenInstrImmediate(REGIMM, rs, BLTZAL, offset); |
BlockTrampolinePoolFor(1); // For associated delay slot. |
} |
@@ -1460,7 +1456,6 @@ void Assembler::bnvc(Register rs, Register rt, int16_t offset) { |
void Assembler::blezalc(Register rt, int16_t offset) { |
DCHECK(IsMipsArchVariant(kMips32r6)); |
DCHECK(!(rt.is(zero_reg))); |
- positions_recorder()->WriteRecordedPositions(); |
GenInstrImmediate(BLEZ, zero_reg, rt, offset, |
CompactBranchType::COMPACT_BRANCH); |
} |
@@ -1469,7 +1464,6 @@ void Assembler::blezalc(Register rt, int16_t offset) { |
void Assembler::bgezalc(Register rt, int16_t offset) { |
DCHECK(IsMipsArchVariant(kMips32r6)); |
DCHECK(!(rt.is(zero_reg))); |
- positions_recorder()->WriteRecordedPositions(); |
GenInstrImmediate(BLEZ, rt, rt, offset, CompactBranchType::COMPACT_BRANCH); |
} |
@@ -1478,7 +1472,6 @@ void Assembler::bgezall(Register rs, int16_t offset) { |
DCHECK(!IsMipsArchVariant(kMips32r6)); |
DCHECK(!(rs.is(zero_reg))); |
BlockTrampolinePoolScope block_trampoline_pool(this); |
- positions_recorder()->WriteRecordedPositions(); |
GenInstrImmediate(REGIMM, rs, BGEZALL, offset); |
BlockTrampolinePoolFor(1); // For associated delay slot. |
} |
@@ -1487,7 +1480,6 @@ void Assembler::bgezall(Register rs, int16_t offset) { |
void Assembler::bltzalc(Register rt, int16_t offset) { |
DCHECK(IsMipsArchVariant(kMips32r6)); |
DCHECK(!(rt.is(zero_reg))); |
- positions_recorder()->WriteRecordedPositions(); |
GenInstrImmediate(BGTZ, rt, rt, offset, CompactBranchType::COMPACT_BRANCH); |
} |
@@ -1495,7 +1487,6 @@ void Assembler::bltzalc(Register rt, int16_t offset) { |
void Assembler::bgtzalc(Register rt, int16_t offset) { |
DCHECK(IsMipsArchVariant(kMips32r6)); |
DCHECK(!(rt.is(zero_reg))); |
- positions_recorder()->WriteRecordedPositions(); |
GenInstrImmediate(BGTZ, zero_reg, rt, offset, |
CompactBranchType::COMPACT_BRANCH); |
} |
@@ -1504,7 +1495,6 @@ void Assembler::bgtzalc(Register rt, int16_t offset) { |
void Assembler::beqzalc(Register rt, int16_t offset) { |
DCHECK(IsMipsArchVariant(kMips32r6)); |
DCHECK(!(rt.is(zero_reg))); |
- positions_recorder()->WriteRecordedPositions(); |
GenInstrImmediate(ADDI, zero_reg, rt, offset, |
CompactBranchType::COMPACT_BRANCH); |
} |
@@ -1513,7 +1503,6 @@ void Assembler::beqzalc(Register rt, int16_t offset) { |
void Assembler::bnezalc(Register rt, int16_t offset) { |
DCHECK(IsMipsArchVariant(kMips32r6)); |
DCHECK(!(rt.is(zero_reg))); |
- positions_recorder()->WriteRecordedPositions(); |
GenInstrImmediate(DADDI, zero_reg, rt, offset, |
CompactBranchType::COMPACT_BRANCH); |
} |
@@ -1572,9 +1561,6 @@ void Assembler::j(int32_t target) { |
void Assembler::jr(Register rs) { |
if (!IsMipsArchVariant(kMips32r6)) { |
BlockTrampolinePoolScope block_trampoline_pool(this); |
- if (rs.is(ra)) { |
- positions_recorder()->WriteRecordedPositions(); |
- } |
GenInstrRegister(SPECIAL, rs, zero_reg, zero_reg, 0, JR); |
BlockTrampolinePoolFor(1); // For associated delay slot. |
} else { |
@@ -1592,7 +1578,6 @@ void Assembler::jal(int32_t target) { |
DCHECK(in_range && ((target & 3) == 0)); |
#endif |
BlockTrampolinePoolScope block_trampoline_pool(this); |
- positions_recorder()->WriteRecordedPositions(); |
GenInstrJump(JAL, (target >> 2) & kImm26Mask); |
BlockTrampolinePoolFor(1); // For associated delay slot. |
} |
@@ -1601,7 +1586,6 @@ void Assembler::jal(int32_t target) { |
void Assembler::jalr(Register rs, Register rd) { |
DCHECK(rs.code() != rd.code()); |
BlockTrampolinePoolScope block_trampoline_pool(this); |
- positions_recorder()->WriteRecordedPositions(); |
GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR); |
BlockTrampolinePoolFor(1); // For associated delay slot. |
} |
@@ -1615,7 +1599,6 @@ void Assembler::jic(Register rt, int16_t offset) { |
void Assembler::jialc(Register rt, int16_t offset) { |
DCHECK(IsMipsArchVariant(kMips32r6)); |
- positions_recorder()->WriteRecordedPositions(); |
GenInstrImmediate(POP76, zero_reg, rt, offset); |
} |