| Index: openssl/crypto/chacha/chacha_vec.c
 | 
| diff --git a/openssl/crypto/chacha/chacha_vec.c b/openssl/crypto/chacha/chacha_vec.c
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| deleted file mode 100644
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| index 274345d56b38663c28e3a001c504dba669c935e8..0000000000000000000000000000000000000000
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| --- a/openssl/crypto/chacha/chacha_vec.c
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| +++ /dev/null
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| @@ -1,352 +0,0 @@
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| -/* ====================================================================
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| - * Copyright (c) 2011-2013 The OpenSSL Project.  All rights reserved.
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| - *
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| - * Redistribution and use in source and binary forms, with or without
 | 
| - * modification, are permitted provided that the following conditions
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| - * are met:
 | 
| - *
 | 
| - * 1. Redistributions of source code must retain the above copyright
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| - *    notice, this list of conditions and the following disclaimer.
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| - *
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| - * 2. Redistributions in binary form must reproduce the above copyright
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| - *    notice, this list of conditions and the following disclaimer in
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| - *    the documentation and/or other materials provided with the
 | 
| - *    distribution.
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| - *
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| - * 3. All advertising materials mentioning features or use of this
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| - *    software must display the following acknowledgment:
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| - *    "This product includes software developed by the OpenSSL Project
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| - *    for use in the OpenSSL Toolkit. (http://www.OpenSSL.org/)"
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| - *
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| - * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to
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| - *    endorse or promote products derived from this software without
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| - *    prior written permission. For written permission, please contact
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| - *    licensing@OpenSSL.org.
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| - *
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| - * 5. Products derived from this software may not be called "OpenSSL"
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| - *    nor may "OpenSSL" appear in their names without prior written
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| - *    permission of the OpenSSL Project.
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| - *
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| - * 6. Redistributions of any form whatsoever must retain the following
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| - *    acknowledgment:
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| - *    "This product includes software developed by the OpenSSL Project
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| - *    for use in the OpenSSL Toolkit (http://www.OpenSSL.org/)"
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| - *
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| - * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY
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| - * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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| - * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE OpenSSL PROJECT OR
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| - * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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| - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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| - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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| - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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| - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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| - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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| - * OF THE POSSIBILITY OF SUCH DAMAGE.
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| - * ====================================================================
 | 
| - */
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| -
 | 
| -/* This implementation is by Ted Krovetz and was submitted to SUPERCOP and
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| - * marked as public domain. It was been altered to allow for non-aligned inputs
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| - * and to allow the block counter to be passed in specifically. */
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| -
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| -#include <string.h>
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| -#include <stdint.h>
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| -#include <openssl/opensslconf.h>
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| -
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| -#if !defined(OPENSSL_NO_CHACHA)
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| -
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| -#include <openssl/chacha.h>
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| -
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| -#ifndef CHACHA_RNDS
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| -#define CHACHA_RNDS 20    /* 8 (high speed), 20 (conservative), 12 (middle) */
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| -#endif
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| -
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| -/* Architecture-neutral way to specify 16-byte vector of ints              */
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| -typedef unsigned vec __attribute__ ((vector_size (16)));
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| -
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| -/* This implementation is designed for Neon, SSE and AltiVec machines. The
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| - * following specify how to do certain vector operations efficiently on
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| - * each architecture, using intrinsics.
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| - * This implementation supports parallel processing of multiple blocks,
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| - * including potentially using general-purpose registers.
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| - */
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| -#if __ARM_NEON__
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| -#include <arm_neon.h>
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| -#define GPR_TOO   1
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| -#define VBPI      2
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| -#define ONE       (vec)vsetq_lane_u32(1,vdupq_n_u32(0),0)
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| -#define LOAD(m)   (vec)(*((vec*)(m)))
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| -#define STORE(m,r) (*((vec*)(m))) = (r)
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| -#define ROTV1(x)  (vec)vextq_u32((uint32x4_t)x,(uint32x4_t)x,1)
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| -#define ROTV2(x)  (vec)vextq_u32((uint32x4_t)x,(uint32x4_t)x,2)
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| -#define ROTV3(x)  (vec)vextq_u32((uint32x4_t)x,(uint32x4_t)x,3)
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| -#define ROTW16(x) (vec)vrev32q_u16((uint16x8_t)x)
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| -#if __clang__
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| -#define ROTW7(x)  (x << ((vec){ 7, 7, 7, 7})) ^ (x >> ((vec){25,25,25,25}))
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| -#define ROTW8(x)  (x << ((vec){ 8, 8, 8, 8})) ^ (x >> ((vec){24,24,24,24}))
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| -#define ROTW12(x) (x << ((vec){12,12,12,12})) ^ (x >> ((vec){20,20,20,20}))
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| -#else
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| -#define ROTW7(x)  (vec)vsriq_n_u32(vshlq_n_u32((uint32x4_t)x,7),(uint32x4_t)x,25)
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| -#define ROTW8(x)  (vec)vsriq_n_u32(vshlq_n_u32((uint32x4_t)x,8),(uint32x4_t)x,24)
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| -#define ROTW12(x) (vec)vsriq_n_u32(vshlq_n_u32((uint32x4_t)x,12),(uint32x4_t)x,20)
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| -#endif
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| -#elif __SSE2__
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| -#include <emmintrin.h>
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| -#define GPR_TOO   0
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| -#if __clang__
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| -#define VBPI      4
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| -#else
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| -#define VBPI      3
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| -#endif
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| -#define ONE       (vec)_mm_set_epi32(0,0,0,1)
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| -#define LOAD(m)   (vec)_mm_loadu_si128((__m128i*)(m))
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| -#define STORE(m,r) _mm_storeu_si128((__m128i*)(m), (__m128i) (r))
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| -#define ROTV1(x)  (vec)_mm_shuffle_epi32((__m128i)x,_MM_SHUFFLE(0,3,2,1))
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| -#define ROTV2(x)  (vec)_mm_shuffle_epi32((__m128i)x,_MM_SHUFFLE(1,0,3,2))
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| -#define ROTV3(x)  (vec)_mm_shuffle_epi32((__m128i)x,_MM_SHUFFLE(2,1,0,3))
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| -#define ROTW7(x)  (vec)(_mm_slli_epi32((__m128i)x, 7) ^ _mm_srli_epi32((__m128i)x,25))
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| -#define ROTW12(x) (vec)(_mm_slli_epi32((__m128i)x,12) ^ _mm_srli_epi32((__m128i)x,20))
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| -#if __SSSE3__
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| -#include <tmmintrin.h>
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| -#define ROTW8(x)  (vec)_mm_shuffle_epi8((__m128i)x,_mm_set_epi8(14,13,12,15,10,9,8,11,6,5,4,7,2,1,0,3))
 | 
| -#define ROTW16(x) (vec)_mm_shuffle_epi8((__m128i)x,_mm_set_epi8(13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2))
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| -#else
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| -#define ROTW8(x)  (vec)(_mm_slli_epi32((__m128i)x, 8) ^ _mm_srli_epi32((__m128i)x,24))
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| -#define ROTW16(x) (vec)(_mm_slli_epi32((__m128i)x,16) ^ _mm_srli_epi32((__m128i)x,16))
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| -#endif
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| -#else
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| -#error -- Implementation supports only machines with neon or SSE2
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| -#endif
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| -
 | 
| -#ifndef REVV_BE
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| -#define REVV_BE(x)  (x)
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| -#endif
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| -
 | 
| -#ifndef REVW_BE
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| -#define REVW_BE(x)  (x)
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| -#endif
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| -
 | 
| -#define BPI      (VBPI + GPR_TOO)  /* Blocks computed per loop iteration   */
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| -
 | 
| -#define DQROUND_VECTORS(a,b,c,d)                \
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| -    a += b; d ^= a; d = ROTW16(d);              \
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| -    c += d; b ^= c; b = ROTW12(b);              \
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| -    a += b; d ^= a; d = ROTW8(d);               \
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| -    c += d; b ^= c; b = ROTW7(b);               \
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| -    b = ROTV1(b); c = ROTV2(c);  d = ROTV3(d);  \
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| -    a += b; d ^= a; d = ROTW16(d);              \
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| -    c += d; b ^= c; b = ROTW12(b);              \
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| -    a += b; d ^= a; d = ROTW8(d);               \
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| -    c += d; b ^= c; b = ROTW7(b);               \
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| -    b = ROTV3(b); c = ROTV2(c); d = ROTV1(d);
 | 
| -
 | 
| -#define QROUND_WORDS(a,b,c,d) \
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| -  a = a+b; d ^= a; d = d<<16 | d>>16; \
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| -  c = c+d; b ^= c; b = b<<12 | b>>20; \
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| -  a = a+b; d ^= a; d = d<< 8 | d>>24; \
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| -  c = c+d; b ^= c; b = b<< 7 | b>>25;
 | 
| -
 | 
| -#define WRITE_XOR(in, op, d, v0, v1, v2, v3)                   \
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| -	STORE(op + d + 0, LOAD(in + d + 0) ^ REVV_BE(v0));      \
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| -	STORE(op + d + 4, LOAD(in + d + 4) ^ REVV_BE(v1));      \
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| -	STORE(op + d + 8, LOAD(in + d + 8) ^ REVV_BE(v2));      \
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| -	STORE(op + d +12, LOAD(in + d +12) ^ REVV_BE(v3));
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| -
 | 
| -#if __ARM_NEON__
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| -/* For ARM, we can't depend on NEON support, so this function is compiled with
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| - * a different name, along with the generic code, and can be enabled at
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| - * run-time. */
 | 
| -void CRYPTO_chacha_20_neon(
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| -#else
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| -void CRYPTO_chacha_20(
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| -#endif
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| -	unsigned char *out,
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| -	const unsigned char *in,
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| -	size_t inlen,
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| -	const unsigned char key[32],
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| -	const unsigned char nonce[8],
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| -	size_t counter)
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| -	{
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| -	unsigned iters, i, *op=(unsigned *)out, *ip=(unsigned *)in, *kp;
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| -#if defined(__ARM_NEON__)
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| -	unsigned *np;
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| -#endif
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| -	vec s0, s1, s2, s3;
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| -#if !defined(__ARM_NEON__) && !defined(__SSE2__)
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| -	__attribute__ ((aligned (16))) unsigned key[8], nonce[4];
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| -#endif
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| -	__attribute__ ((aligned (16))) unsigned chacha_const[] =
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| -		{0x61707865,0x3320646E,0x79622D32,0x6B206574};
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| -#if defined(__ARM_NEON__) || defined(__SSE2__)
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| -	kp = (unsigned *)key;
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| -#else
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| -	((vec *)key)[0] = REVV_BE(((vec *)key)[0]);
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| -	((vec *)key)[1] = REVV_BE(((vec *)key)[1]);
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| -	nonce[0] = REVW_BE(((unsigned *)nonce)[0]);
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| -	nonce[1] = REVW_BE(((unsigned *)nonce)[1]);
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| -	nonce[2] = REVW_BE(((unsigned *)nonce)[2]);
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| -	nonce[3] = REVW_BE(((unsigned *)nonce)[3]);
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| -	kp = (unsigned *)key;
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| -	np = (unsigned *)nonce;
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| -#endif
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| -#if defined(__ARM_NEON__)
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| -	np = (unsigned*) nonce;
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| -#endif
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| -	s0 = LOAD(chacha_const);
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| -	s1 = LOAD(&((vec*)kp)[0]);
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| -	s2 = LOAD(&((vec*)kp)[1]);
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| -	s3 = (vec){
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| -		counter & 0xffffffff,
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| -#if __ARM_NEON__
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| -		0,  /* can't right-shift 32 bits on a 32-bit system. */
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| -#else
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| -		counter >> 32,
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| -#endif
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| -		((uint32_t*)nonce)[0],
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| -		((uint32_t*)nonce)[1]
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| -	};
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| -
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| -	for (iters = 0; iters < inlen/(BPI*64); iters++)
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| -		{
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| -#if GPR_TOO
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| -		register unsigned x0, x1, x2, x3, x4, x5, x6, x7, x8,
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| -				  x9, x10, x11, x12, x13, x14, x15;
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| -#endif
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| -#if VBPI > 2
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| -		vec v8,v9,v10,v11;
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| -#endif
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| -#if VBPI > 3
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| -		vec v12,v13,v14,v15;
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| -#endif
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| -
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| -		vec v0,v1,v2,v3,v4,v5,v6,v7;
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| -		v4 = v0 = s0; v5 = v1 = s1; v6 = v2 = s2; v3 = s3;
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| -		v7 = v3 + ONE;
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| -#if VBPI > 2
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| -		v8 = v4; v9 = v5; v10 = v6;
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| -		v11 =  v7 + ONE;
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| -#endif
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| -#if VBPI > 3
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| -		v12 = v8; v13 = v9; v14 = v10;
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| -		v15 = v11 + ONE;
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| -#endif
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| -#if GPR_TOO
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| -		x0 = chacha_const[0]; x1 = chacha_const[1];
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| -		x2 = chacha_const[2]; x3 = chacha_const[3];
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| -		x4 = kp[0]; x5 = kp[1]; x6  = kp[2]; x7  = kp[3];
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| -		x8 = kp[4]; x9 = kp[5]; x10 = kp[6]; x11 = kp[7];
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| -		x12 = counter+BPI*iters+(BPI-1); x13 = 0;
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| -		x14 = np[0]; x15 = np[1];
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| -#endif
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| -		for (i = CHACHA_RNDS/2; i; i--)
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| -			{
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| -			DQROUND_VECTORS(v0,v1,v2,v3)
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| -			DQROUND_VECTORS(v4,v5,v6,v7)
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| -#if VBPI > 2
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| -			DQROUND_VECTORS(v8,v9,v10,v11)
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| -#endif
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| -#if VBPI > 3
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| -			DQROUND_VECTORS(v12,v13,v14,v15)
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| -#endif
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| -#if GPR_TOO
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| -			QROUND_WORDS( x0, x4, x8,x12)
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| -			QROUND_WORDS( x1, x5, x9,x13)
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| -			QROUND_WORDS( x2, x6,x10,x14)
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| -			QROUND_WORDS( x3, x7,x11,x15)
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| -			QROUND_WORDS( x0, x5,x10,x15)
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| -			QROUND_WORDS( x1, x6,x11,x12)
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| -			QROUND_WORDS( x2, x7, x8,x13)
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| -			QROUND_WORDS( x3, x4, x9,x14)
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| -#endif
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| -			}
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| -
 | 
| -		WRITE_XOR(ip, op, 0, v0+s0, v1+s1, v2+s2, v3+s3)
 | 
| -		s3 += ONE;
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| -		WRITE_XOR(ip, op, 16, v4+s0, v5+s1, v6+s2, v7+s3)
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| -		s3 += ONE;
 | 
| -#if VBPI > 2
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| -		WRITE_XOR(ip, op, 32, v8+s0, v9+s1, v10+s2, v11+s3)
 | 
| -		s3 += ONE;
 | 
| -#endif
 | 
| -#if VBPI > 3
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| -		WRITE_XOR(ip, op, 48, v12+s0, v13+s1, v14+s2, v15+s3)
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| -		s3 += ONE;
 | 
| -#endif
 | 
| -		ip += VBPI*16;
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| -		op += VBPI*16;
 | 
| -#if GPR_TOO
 | 
| -		op[0]  = REVW_BE(REVW_BE(ip[0])  ^ (x0  + chacha_const[0]));
 | 
| -		op[1]  = REVW_BE(REVW_BE(ip[1])  ^ (x1  + chacha_const[1]));
 | 
| -		op[2]  = REVW_BE(REVW_BE(ip[2])  ^ (x2  + chacha_const[2]));
 | 
| -		op[3]  = REVW_BE(REVW_BE(ip[3])  ^ (x3  + chacha_const[3]));
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| -		op[4]  = REVW_BE(REVW_BE(ip[4])  ^ (x4  + kp[0]));
 | 
| -		op[5]  = REVW_BE(REVW_BE(ip[5])  ^ (x5  + kp[1]));
 | 
| -		op[6]  = REVW_BE(REVW_BE(ip[6])  ^ (x6  + kp[2]));
 | 
| -		op[7]  = REVW_BE(REVW_BE(ip[7])  ^ (x7  + kp[3]));
 | 
| -		op[8]  = REVW_BE(REVW_BE(ip[8])  ^ (x8  + kp[4]));
 | 
| -		op[9]  = REVW_BE(REVW_BE(ip[9])  ^ (x9  + kp[5]));
 | 
| -		op[10] = REVW_BE(REVW_BE(ip[10]) ^ (x10 + kp[6]));
 | 
| -		op[11] = REVW_BE(REVW_BE(ip[11]) ^ (x11 + kp[7]));
 | 
| -		op[12] = REVW_BE(REVW_BE(ip[12]) ^ (x12 + counter+BPI*iters+(BPI-1)));
 | 
| -		op[13] = REVW_BE(REVW_BE(ip[13]) ^ (x13));
 | 
| -		op[14] = REVW_BE(REVW_BE(ip[14]) ^ (x14 + np[0]));
 | 
| -		op[15] = REVW_BE(REVW_BE(ip[15]) ^ (x15 + np[1]));
 | 
| -		s3 += ONE;
 | 
| -		ip += 16;
 | 
| -		op += 16;
 | 
| -#endif
 | 
| -		}
 | 
| -
 | 
| -	for (iters = inlen%(BPI*64)/64; iters != 0; iters--)
 | 
| -		{
 | 
| -		vec v0 = s0, v1 = s1, v2 = s2, v3 = s3;
 | 
| -		for (i = CHACHA_RNDS/2; i; i--)
 | 
| -			{
 | 
| -			DQROUND_VECTORS(v0,v1,v2,v3);
 | 
| -			}
 | 
| -		WRITE_XOR(ip, op, 0, v0+s0, v1+s1, v2+s2, v3+s3)
 | 
| -		s3 += ONE;
 | 
| -		ip += 16;
 | 
| -		op += 16;
 | 
| -		}
 | 
| -
 | 
| -	inlen = inlen % 64;
 | 
| -	if (inlen)
 | 
| -		{
 | 
| -		__attribute__ ((aligned (16))) vec buf[4];
 | 
| -		vec v0,v1,v2,v3;
 | 
| -		v0 = s0; v1 = s1; v2 = s2; v3 = s3;
 | 
| -		for (i = CHACHA_RNDS/2; i; i--)
 | 
| -			{
 | 
| -			DQROUND_VECTORS(v0,v1,v2,v3);
 | 
| -			}
 | 
| -
 | 
| -		if (inlen >= 16)
 | 
| -			{
 | 
| -			STORE(op + 0, LOAD(ip + 0) ^ REVV_BE(v0 + s0));
 | 
| -			if (inlen >= 32)
 | 
| -				{
 | 
| -				STORE(op + 4, LOAD(ip + 4) ^ REVV_BE(v1 + s1));
 | 
| -				if (inlen >= 48)
 | 
| -					{
 | 
| -					STORE(op + 8, LOAD(ip +  8) ^
 | 
| -						      REVV_BE(v2 + s2));
 | 
| -					buf[3] = REVV_BE(v3 + s3);
 | 
| -					}
 | 
| -				else
 | 
| -					buf[2] = REVV_BE(v2 + s2);
 | 
| -				}
 | 
| -			else
 | 
| -				buf[1] = REVV_BE(v1 + s1);
 | 
| -			}
 | 
| -		else
 | 
| -			buf[0] = REVV_BE(v0 + s0);
 | 
| -
 | 
| -		for (i=inlen & ~15; i<inlen; i++)
 | 
| -			((char *)op)[i] = ((char *)ip)[i] ^ ((char *)buf)[i];
 | 
| -		}
 | 
| -	}
 | 
| -
 | 
| -#endif  /* !OPENSSL_NO_CHACHA */
 | 
| 
 |