Calling convention for MIPS32

src/IceInstMIPS32.def

Index: src/IceInstMIPS32.def
diff --git a/src/IceInstMIPS32.def b/src/IceInstMIPS32.def
index 6120a47322e483595bf4fa6a93837a572f29c521..b2bd1cd8a804da92734eee757031ebcf050f39f2 100644
--- a/src/IceInstMIPS32.def
+++ b/src/IceInstMIPS32.def
@@ -123,9 +123,11 @@
   X(Reg_F9,       9,   "f9",    1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F9))          \
   X(Reg_F10,      10,  "f10",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F10))         \
   X(Reg_F11,      11,  "f11",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F11))         \
-  X(Reg_F12,      12,  "f12",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F12))         \
+  X(Reg_F12,      12,  "f12",   1,0,0,0, 0,0,1,0,0,                            \
+  ALIASES2(Reg_F12, Reg_F12F13))                                               \

[Jim Stichnoth, 2016/06/10 23:03:46]

I would prepend 2 spaces so it lines up with Reg_F12 above.

   X(Reg_F13,      13,  "f13",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F13))         \

[Jim Stichnoth, 2016/06/10 23:03:46]

I think Reg_F12F13 should also be listed here.

In fact, all these registers should have their register pair listed as an alias.

The alias matrix should be symmetric, i.e. if i is an alias of j, then j should
be an alias of i.  I thought at least one other target validated this, but I
can't find any evidence of that in the current code...

-  X(Reg_F14,      14,  "f14",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F14))         \
+  X(Reg_F14,      14,  "f14",   1,0,0,0, 0,0,1,0,0,                            \
+  ALIASES2(Reg_F14, Reg_F14F15))                                               \
   X(Reg_F15,      15,  "f15",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F15))         \
   X(Reg_F16,      16,  "f16",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F16))         \
   X(Reg_F17,      17,  "f17",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F17))         \