Calling convention for MIPS32

src/IceInstMIPS32.def

 //===- subzero/src/IceInstMIPS32.def - X-Macros for MIPS insts --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines properties of MIPS32 instructions in the form of x-macros.
@@ skipping 105 matching lines @@
   X(Reg_F2,       2,   "f2",    1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F2))          \
   X(Reg_F3,       3,   "f3",    1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F3))          \
   X(Reg_F4,       4,   "f4",    1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F4))          \
   X(Reg_F5,       5,   "f5",    1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F5))          \
   X(Reg_F6,       6,   "f6",    1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F6))          \
   X(Reg_F7,       7,   "f7",    1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F7))          \
   X(Reg_F8,       8,   "f8",    1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F8))          \
   X(Reg_F9,       9,   "f9",    1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F9))          \
   X(Reg_F10,      10,  "f10",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F10))         \
   X(Reg_F11,      11,  "f11",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F11))         \
-  X(Reg_F12,      12,  "f12",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F12))         \
+  X(Reg_F12,      12,  "f12",   1,0,0,0, 0,0,1,0,0,                            \
+  ALIASES2(Reg_F12, Reg_F12F13))                                               \

[Jim Stichnoth, 2016/06/10 23:03:46]

I would prepend 2 spaces so it lines up with Reg_F12 above.

   X(Reg_F13,      13,  "f13",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F13))         \

[Jim Stichnoth, 2016/06/10 23:03:46]

I think Reg_F12F13 should also be listed here.

In fact, all these registers should have their register pair listed as an alias.

The alias matrix should be symmetric, i.e. if i is an alias of j, then j should
be an alias of i.  I thought at least one other target validated this, but I
can't find any evidence of that in the current code...

-  X(Reg_F14,      14,  "f14",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F14))         \
+  X(Reg_F14,      14,  "f14",   1,0,0,0, 0,0,1,0,0,                            \
+  ALIASES2(Reg_F14, Reg_F14F15))                                               \
   X(Reg_F15,      15,  "f15",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F15))         \
   X(Reg_F16,      16,  "f16",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F16))         \
   X(Reg_F17,      17,  "f17",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F17))         \
   X(Reg_F18,      18,  "f18",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F18))         \
   X(Reg_F19,      19,  "f19",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F19))         \
   X(Reg_F20,      20,  "f20",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F20))         \
   X(Reg_F21,      21,  "f21",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F21))         \
   X(Reg_F22,      22,  "f22",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F22))         \
   X(Reg_F23,      23,  "f23",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F23))         \
   X(Reg_F24,      24,  "f24",   1,0,0,0, 0,0,1,0,0, ALIASES1(Reg_F24))         \
@@ skipping 114 matching lines @@
   X(NEZ,   EQZ,   "nez") /* signed not equal to zero */                        \
   X(GEZ,   LTZ,   "gez") /* signed greater than or equal to zero */            \
   X(LTZ,   GEZ,   "ltz") /* signed less than to zero */                        \
   X(GTZ,   LEZ,   "gtz") /* signed greater than to zero */                     \
   X(LEZ,   GTZ,   "lez") /* signed less than or equal to zero */               \
   X(AL,    kNone, "")    /* always (unconditional) */                          \
   X(kNone, kNone, "??")  /* special condition / none */
 //#define X(tag, opp, emit)
 
 #endif // SUBZERO_SRC_ICEINSTMIPS32_DEF