Add FloatRegister names to RegisterConfiguration.

src/assembler.cc

Index: src/assembler.cc
diff --git a/src/assembler.cc b/src/assembler.cc
index 17cd56be8064b1eb518e2ee2e92118eeda9ccbfb..30106b75520acbf96f6327fc6c118981e5325e75 100644
--- a/src/assembler.cc
+++ b/src/assembler.cc
@@ -130,7 +130,6 @@ bool Register::IsAllocatable() const {
               ->allocatable_general_codes_mask()) != 0;
 }
 
-
 const char* DoubleRegister::ToString() {
   // This is the mapping of allocation indices to registers.
   DCHECK(reg_code >= 0 && reg_code < kMaxNumRegisters);
@@ -145,6 +144,23 @@ bool DoubleRegister::IsAllocatable() const {
               ->allocatable_double_codes_mask()) != 0;
 }
 
+// FloatRegister is only a distinct type on ARM. On all other platforms it's
+// typedef'ed to DoubleRegister.
+#if V8_TARGET_ARCH_ARM
+const char* FloatRegister::ToString() {
+  // This is the mapping of allocation indices to registers.
+  DCHECK(reg_code >= 0 && reg_code < kMaxNumRegisters);
+  return RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT)
+      ->GetFloatRegisterName(reg_code);
+}
+
+bool FloatRegister::IsAllocatable() const {
+  // TODO(bbudge) Update this once RegisterConfigutation handles aliasing.
+  return ((1 << reg_code) &
+          RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT)
+              ->allocatable_double_codes_mask()) != 0;
+}
+#endif  // V8_TARGET_ARCH_ARM
 
 // -----------------------------------------------------------------------------
 // Common double constants.