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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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123 ->GetGeneralRegisterName(reg_code); | 123 ->GetGeneralRegisterName(reg_code); |
124 } | 124 } |
125 | 125 |
126 | 126 |
127 bool Register::IsAllocatable() const { | 127 bool Register::IsAllocatable() const { |
128 return ((1 << reg_code) & | 128 return ((1 << reg_code) & |
129 RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT) | 129 RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT) |
130 ->allocatable_general_codes_mask()) != 0; | 130 ->allocatable_general_codes_mask()) != 0; |
131 } | 131 } |
132 | 132 |
133 | |
134 const char* DoubleRegister::ToString() { | 133 const char* DoubleRegister::ToString() { |
135 // This is the mapping of allocation indices to registers. | 134 // This is the mapping of allocation indices to registers. |
136 DCHECK(reg_code >= 0 && reg_code < kMaxNumRegisters); | 135 DCHECK(reg_code >= 0 && reg_code < kMaxNumRegisters); |
137 return RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT) | 136 return RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT) |
138 ->GetDoubleRegisterName(reg_code); | 137 ->GetDoubleRegisterName(reg_code); |
139 } | 138 } |
140 | 139 |
141 | 140 |
142 bool DoubleRegister::IsAllocatable() const { | 141 bool DoubleRegister::IsAllocatable() const { |
143 return ((1 << reg_code) & | 142 return ((1 << reg_code) & |
144 RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT) | 143 RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT) |
145 ->allocatable_double_codes_mask()) != 0; | 144 ->allocatable_double_codes_mask()) != 0; |
146 } | 145 } |
147 | 146 |
| 147 // FloatRegister is only a distinct type on ARM. On all other platforms it's |
| 148 // typedef'ed to DoubleRegister. |
| 149 #if V8_TARGET_ARCH_ARM |
| 150 const char* FloatRegister::ToString() { |
| 151 // This is the mapping of allocation indices to registers. |
| 152 DCHECK(reg_code >= 0 && reg_code < kMaxNumRegisters); |
| 153 return RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT) |
| 154 ->GetFloatRegisterName(reg_code); |
| 155 } |
| 156 |
| 157 bool FloatRegister::IsAllocatable() const { |
| 158 // TODO(bbudge) Update this once RegisterConfigutation handles aliasing. |
| 159 return ((1 << reg_code) & |
| 160 RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT) |
| 161 ->allocatable_double_codes_mask()) != 0; |
| 162 } |
| 163 #endif // V8_TARGET_ARCH_ARM |
148 | 164 |
149 // ----------------------------------------------------------------------------- | 165 // ----------------------------------------------------------------------------- |
150 // Common double constants. | 166 // Common double constants. |
151 | 167 |
152 struct DoubleConstant BASE_EMBEDDED { | 168 struct DoubleConstant BASE_EMBEDDED { |
153 double min_int; | 169 double min_int; |
154 double one_half; | 170 double one_half; |
155 double minus_one_half; | 171 double minus_one_half; |
156 double negative_infinity; | 172 double negative_infinity; |
157 double the_hole_nan; | 173 double the_hole_nan; |
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2088 | 2104 |
2089 | 2105 |
2090 void Assembler::DataAlign(int m) { | 2106 void Assembler::DataAlign(int m) { |
2091 DCHECK(m >= 2 && base::bits::IsPowerOfTwo32(m)); | 2107 DCHECK(m >= 2 && base::bits::IsPowerOfTwo32(m)); |
2092 while ((pc_offset() & (m - 1)) != 0) { | 2108 while ((pc_offset() & (m - 1)) != 0) { |
2093 db(0); | 2109 db(0); |
2094 } | 2110 } |
2095 } | 2111 } |
2096 } // namespace internal | 2112 } // namespace internal |
2097 } // namespace v8 | 2113 } // namespace v8 |
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