[Subzero][MIPS32] Implement i1 cast operations

[Subzero][MIPS32] Implement i1 cast operations

R=stichnot@chromium.org

Committed: https://gerrit.chromium.org/gerrit/gitweb?p=native_client/pnacl-subzero.git;a=commit;h=e160ed9263869cb802f7ab4eadce709413438d95

[sagar.thakur, 2016-05-27 06:56:48]

sagar.thakur@imgtec.com changed reviewers:
+ eholk@chromium.org, jpp@chromium.org, kschimpf@google.com,
stichnot@chromium.org

[Jim Stichnoth, 2016-05-27 21:59:03]

https://codereview.chromium.org/2017043002/diff/1/src/IceTargetLoweringMIPS32...
File src/IceTargetLoweringMIPS32.cpp (right):

https://codereview.chromium.org/2017043002/diff/1/src/IceTargetLoweringMIPS32...
src/IceTargetLoweringMIPS32.cpp:1075: _andi(Dest, Src0R, Mask);
Here and above.

Dest is a normal program variable, not an infinite-weight temporary.  As such,
there is no guarantee that Dest will get a physical register, and so Dest may
ultimately resolve to a stack location (memory operand).  In that case, this
generates an illegal instruction.

Doing "T=makeReg()" and "_mov(Dest,T)" makes sure the dest of the "and"
instruction is a physical register and therefore a legal instruction.  In O2
mode, the register allocator will likely allocate the same register to Dest and
T, making "_mov(Dest,T)" a redundant assignment that is trivially elided.

If you change the RUN command in the .ll file to use -Om1 instead of -O2, you
will see that invalid code is generated and the llvm-mc assembler complains.

[sagar.thakur, 2016-05-30 10:46:02]

https://codereview.chromium.org/2017043002/diff/1/src/IceTargetLoweringMIPS32...
File src/IceTargetLoweringMIPS32.cpp (right):

https://codereview.chromium.org/2017043002/diff/1/src/IceTargetLoweringMIPS32...
src/IceTargetLoweringMIPS32.cpp:1075: _andi(Dest, Src0R, Mask);
On 2016/05/27 21:59:03, stichnot wrote:
> Here and above.
> 
> Dest is a normal program variable, not an infinite-weight temporary.  As such,
> there is no guarantee that Dest will get a physical register, and so Dest may
> ultimately resolve to a stack location (memory operand).  In that case, this
> generates an illegal instruction.
> 
> Doing "T=makeReg()" and "_mov(Dest,T)" makes sure the dest of the "and"
> instruction is a physical register and therefore a legal instruction.  In O2
> mode, the register allocator will likely allocate the same register to Dest
and
> T, making "_mov(Dest,T)" a redundant assignment that is trivially elided.
> 
> If you change the RUN command in the .ll file to use -Om1 instead of -O2, you
> will see that invalid code is generated and the llvm-mc assembler complains.

Done. Added temporaries in all places were instruction expects physical
register. This will avoid illegal instruction in -Om1

[Jim Stichnoth, 2016-05-30 14:54:42]

lgtm

[Jim Stichnoth, 2016-05-30 14:54:51]

Description was changed from

==========
[Subzero][MIPS32] Implement i1 cast operations
==========

to

==========
[Subzero][MIPS32] Implement i1 cast operations

R=stichnot@chromium.org

Committed:
https://gerrit.chromium.org/gerrit/gitweb?p=native_client/pnacl-subzero.git;a...
==========

[Jim Stichnoth, 2016-05-30 14:54:52]

Committed patchset #2 (id:20001) manually as
e160ed9263869cb802f7ab4eadce709413438d95 (presubmit successful).