[Subzero][MIPS32] Implement i1 cast operations

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 991 matching lines @@
   }
 }
 
 void TargetMIPS32::lowerCast(const InstCast *Instr) {
   InstCast::OpKind CastKind = Instr->getCastKind();
   Variable *Dest = Instr->getDest();
   Operand *Src0 = legalizeUndef(Instr->getSrc(0));
   const Type DestTy = Dest->getType();
   const Type Src0Ty = Src0->getType();
   const uint32_t ShiftAmount =
-      INT32_BITS - (CHAR_BITS * typeWidthInBytes(Src0Ty));
-  const uint32_t Mask = (1 << (CHAR_BITS * typeWidthInBytes(Src0Ty))) - 1;
+      (Src0Ty == IceType_i1
+           ? INT32_BITS - 1
+           : INT32_BITS - (CHAR_BITS * typeWidthInBytes(Src0Ty)));
+  const uint32_t Mask =
+      (Src0Ty == IceType_i1
+           ? 1
+           : (1 << (CHAR_BITS * typeWidthInBytes(Src0Ty))) - 1);
 
-  if (isVectorType(DestTy) || Src0->getType() == IceType_i1) {
+  if (isVectorType(DestTy)) {
     UnimplementedLoweringError(this, Instr);
     return;
   }
   switch (CastKind) {
   default:
     Func->setError("Cast type not supported");
     return;
   case InstCast::Sext: {
     if (DestTy == IceType_i64) {
       auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
       auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *Src0R = legalizeToReg(Src0);
       Variable *T_Lo = I32Reg();
-      if (Src0Ty == IceType_i32) {
-        _mov(DestLo, Src0R);
+      if (Src0Ty == IceType_i1) {
+        _sll(T_Lo, Src0R, INT32_BITS - 1);
+        _sra(DestLo, T_Lo, INT32_BITS - 1);
+        _mov(DestHi, DestLo);
       } else if (Src0Ty == IceType_i8 || Src0Ty == IceType_i16) {
         _sll(T_Lo, Src0R, ShiftAmount);
         _sra(DestLo, T_Lo, ShiftAmount);
+        _sra(DestHi, DestLo, INT32_BITS - 1);
+      } else if (Src0Ty == IceType_i32) {
+        _mov(DestLo, Src0R);
+        _sra(DestHi, DestLo, INT32_BITS - 1);
       }
-      _sra(DestHi, DestLo, INT32_BITS - 1);
     } else {
       Variable *Src0R = legalizeToReg(Src0);
       Variable *T = makeReg(DestTy);
-      if (Src0Ty == IceType_i8 || Src0Ty == IceType_i16) {
+      if (Src0Ty == IceType_i8 || Src0Ty == IceType_i16 ||
+          Src0Ty == IceType_i1) {
         _sll(T, Src0R, ShiftAmount);
         _sra(Dest, T, ShiftAmount);
       }
     }
     break;
   }
   case InstCast::Zext: {
     if (DestTy == IceType_i64) {
       auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
       auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *Src0R = legalizeToReg(Src0);
 
-      switch (Src0Ty) {
-      default: { assert(Src0Ty != IceType_i64); } break;
-      case IceType_i32:
+      if (Src0Ty == IceType_i8 || Src0Ty == IceType_i16 || Src0Ty == IceType_i1)
+        _andi(DestLo, Src0R, Mask);
+      else if (Src0Ty == IceType_i32)
         _mov(DestLo, Src0R);
-        break;
-      case IceType_i8:
-      case IceType_i16:
-        _andi(DestLo, Src0R, Mask);
-        break;
-      }
+      else
+        assert(Src0Ty != IceType_i64);
 
       auto *Zero = getZero();
       _addiu(DestHi, Zero, 0);
     } else {
       Variable *Src0R = legalizeToReg(Src0);
-      Variable *T = makeReg(DestTy);
-      if (Src0Ty == IceType_i8 || Src0Ty == IceType_i16)
-        _andi(T, Src0R, Mask);
-      _mov(Dest, T);
+      if (Src0Ty == IceType_i8 || Src0Ty == IceType_i16 || Src0Ty == IceType_i1)
+        _andi(Dest, Src0R, Mask);

[Jim Stichnoth, 2016/05/27 21:59:03]

Here and above.

Dest is a normal program variable, not an infinite-weight temporary.  As such,
there is no guarantee that Dest will get a physical register, and so Dest may
ultimately resolve to a stack location (memory operand).  In that case, this
generates an illegal instruction.

Doing "T=makeReg()" and "_mov(Dest,T)" makes sure the dest of the "and"
instruction is a physical register and therefore a legal instruction.  In O2
mode, the register allocator will likely allocate the same register to Dest and
T, making "_mov(Dest,T)" a redundant assignment that is trivially elided.

If you change the RUN command in the .ll file to use -Om1 instead of -O2, you
will see that invalid code is generated and the llvm-mc assembler complains.

[sagar.thakur, 2016/05/30 10:46:02]

Done. Added temporaries in all places were instruction expects physical
register. This will avoid illegal instruction in -Om1

     }
     break;
   }
   case InstCast::Trunc: {
     if (Src0Ty == IceType_i64)
       Src0 = loOperand(Src0);
     Variable *Src0R = legalizeToReg(Src0);
     Variable *T = makeReg(DestTy);
     _mov(T, Src0R);
     _mov(Dest, T);
@@ skipping 565 matching lines @@
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice