Subzero, MIPS32: Introduction of floating point registers

src/IceInstMIPS32.h

Index: src/IceInstMIPS32.h
diff --git a/src/IceInstMIPS32.h b/src/IceInstMIPS32.h
index 85f268e8ce9ccaab77b4a2f58bf8966570a2f50f..e5f3849004075c442ef1a6c4be01dfb6ebdbc621 100644
--- a/src/IceInstMIPS32.h
+++ b/src/IceInstMIPS32.h
@@ -127,9 +127,11 @@ public:
     La,
     Label,
     Lui,
+    Mfc1,
     Mfhi,
     Mflo,
     Mov, // actually a pseudo op for addi rd, rs, 0
+    Mtc1,
     Mthi,
     Mtlo,
     Mul,
@@ -172,6 +174,8 @@ public:
                                   const Cfg *Func);
   static void emitUnaryopGPRTLoHi(const char *Opcode, const InstMIPS32 *Inst,
                                   const Cfg *Func);
+  static void emitTwoAddr(const char *Opcode, const InstMIPS32 *Inst,
+                          const Cfg *Func);
   static void emitThreeAddr(const char *Opcode, const InstMIPS32 *Inst,
                             const Cfg *Func);
   static void emitThreeAddrLoHi(const char *Opcode, const InstMIPS32 *Inst,
@@ -256,6 +260,50 @@ private:
   static const char *Opcode;
 };
 
+/// Instructions of the form opcode reg, reg.
+template <InstMIPS32::InstKindMIPS32 K>
+class InstMIPS32TwoAddrGPR : public InstMIPS32 {
+  InstMIPS32TwoAddrGPR() = delete;
+  InstMIPS32TwoAddrGPR(const InstMIPS32TwoAddrGPR &) = delete;
+  InstMIPS32TwoAddrGPR &operator=(const InstMIPS32TwoAddrGPR &) = delete;
+
+public:
+  static InstMIPS32TwoAddrGPR *create(Cfg *Func, Variable *Dest,
+                                        Variable *Src0) {
+    return new (Func->allocate<InstMIPS32TwoAddrGPR>())
+        InstMIPS32TwoAddrGPR(Func, Dest, Src0);
+  }
+  void emit(const Cfg *Func) const override {
+    if (!BuildDefs::dump())
+      return;
+    emitTwoAddr(Opcode, this, Func);
+  }
+  void emitIAS(const Cfg *Func) const override {
+    (void)Func;
+    llvm_unreachable("Not yet implemented");
+  }
+
+  void dump(const Cfg *Func) const override {
+    if (!BuildDefs::dump())
+      return;
+    Ostream &Str = Func->getContext()->getStrDump();
+    dumpDest(Func);
+    Str << " = ";
+    dumpOpcode(Str, Opcode, getDest()->getType());
+    Str << " ";
+    dumpSources(Func);
+  }
+  static bool classof(const Inst *Inst) { return isClassof(Inst, K); }
+
+private:
+  InstMIPS32TwoAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0)
+      : InstMIPS32(Func, K, 2, Dest) {

[Jim Stichnoth, 2016/05/19 23:12:25]

The "2" is the max number of src operands.  I think it should be 1 here since
there is just a single addSource() call, also the emit routine asserts there is
just one src operand.

(This is in contrast to 2-operand instructions where one operand doubles as the
dest variable, like "opc a, b" with semantics "a = a opc b", in which case the
dest variable also needs to be added as a src operand.)

[obucinac, 2016/05/27 11:13:18]

Done.

+    addSource(Src0);
+  }
+
+  static const char *Opcode;
+};
+
 /// Instructions of the form x := y op z. May have the side-effect of setting
 /// status flags.
 template <InstMIPS32::InstKindMIPS32 K>
@@ -472,8 +520,10 @@ using InstMIPS32And = InstMIPS32ThreeAddrGPR<InstMIPS32::And>;
 using InstMIPS32Andi = InstMIPS32Imm16<InstMIPS32::Andi>;
 using InstMIPS32Lui = InstMIPS32Imm16<InstMIPS32::Lui>;
 using InstMIPS32La = InstMIPS32UnaryopGPR<InstMIPS32::La>;
+using InstMIPS32Mfc1 = InstMIPS32TwoAddrGPR<InstMIPS32::Mfc1>;
 using InstMIPS32Mfhi = InstMIPS32UnaryopGPR<InstMIPS32::Mfhi>;
 using InstMIPS32Mflo = InstMIPS32UnaryopGPR<InstMIPS32::Mflo>;
+using InstMIPS32Mtc1 = InstMIPS32TwoAddrGPR<InstMIPS32::Mtc1>;
 using InstMIPS32Mthi = InstMIPS32UnaryopGPR<InstMIPS32::Mthi>;
 using InstMIPS32Mtlo = InstMIPS32UnaryopGPR<InstMIPS32::Mtlo>;
 using InstMIPS32Mul = InstMIPS32ThreeAddrGPR<InstMIPS32::Mul>;