Subzero, MIPS32: Introduction of floating point registers

src/IceInstMIPS32.def

Index: src/IceInstMIPS32.def
diff --git a/src/IceInstMIPS32.def b/src/IceInstMIPS32.def
index 99b58e96bdf99b6ec518d13bbd754e0e4110bf7d..66d86bd77dceff46303e04f55a60f4779aadc597 100644
--- a/src/IceInstMIPS32.def
+++ b/src/IceInstMIPS32.def
@@ -105,13 +105,45 @@
     ALIASES1(Reg_RA))                                                          \
   X(Reg_LO,       0,   "lo",    0, 0, 0, 0, 0, 0, 0, 0, 0,                     \
     ALIASES2(Reg_LO, Reg_LOHI))                                                \
-  X(Reg_HI,       0,  "hi",     0, 0, 0, 0, 0, 0, 0, 0, 0,                     \
+  X(Reg_HI,       0,   "hi",    0, 0, 0, 0, 0, 0, 0, 0, 0,                     \
    ALIASES2(Reg_HI, Reg_LOHI))
-//#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
-//          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
-// TODO(reed kotler): List FP registers etc.
-// Be able to grab even registers, and the corresponding odd register
-// for each even register.
+
+#define REGMIPS32_FPR_TABLE                                                    \
+  /* val, encode, name, scratch, preserved, stackptr, frameptr,                \
+     isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */                 \
+  X(Reg_F0,       0,   "f0",    1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F0))   \

[Jim Stichnoth, 2016/05/19 23:12:25]

This is just a suggestion:

With so many columns, I sometimes find it hard to figure out exactly which
column is which, within a given row.  I find it easier if I can construct some
kind of grouping through use of space characters.  For example:

  /* ... name, scratch,preserved,stackptr,frameptr, isInt,isI64Pair, ... */
  X(..., "f0", 1,0,0,0,0, 0,0,1, ...)

See for example IceInstX8632.def .

[obucinac, 2016/05/27 11:13:18]

Acknowledged.

+  X(Reg_F1,       1,   "f1",    1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F1))   \
+  X(Reg_F2,       2,   "f2",    1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F2))   \
+  X(Reg_F3,       3,   "f3",    1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F3))   \
+  X(Reg_F4,       4,   "f4",    1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F4))   \
+  X(Reg_F5,       5,   "f5",    1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F5))   \
+  X(Reg_F6,       6,   "f6",    1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F6))   \
+  X(Reg_F7,       7,   "f7",    1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F7))   \
+  X(Reg_F8,       8,   "f8",    1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F8))   \
+  X(Reg_F9,       9,   "f9",    1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F9))   \
+  X(Reg_F10,      10,  "f10",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F10))  \
+  X(Reg_F11,      11,  "f11",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F11))  \
+  X(Reg_F12,      12,  "f12",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F12))  \
+  X(Reg_F13,      13,  "f13",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F13))  \
+  X(Reg_F14,      14,  "f14",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F14))  \
+  X(Reg_F15,      15,  "f15",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F15))  \
+  X(Reg_F16,      16,  "f16",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F16))  \
+  X(Reg_F17,      17,  "f17",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F17))  \
+  X(Reg_F18,      18,  "f18",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F18))  \
+  X(Reg_F19,      19,  "f19",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F19))  \
+  X(Reg_F20,      20,  "f20",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F20))  \
+  X(Reg_F21,      21,  "f21",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F21))  \
+  X(Reg_F22,      22,  "f22",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F22))  \
+  X(Reg_F23,      22,  "f23",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F23))  \

[Jim Stichnoth, 2016/05/19 23:12:25]

Numbering got off here.  The 22 should be 23, and similar below.

[obucinac, 2016/05/27 11:13:18]

Done.

+  X(Reg_F24,      23,  "f24",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F24))  \
+  X(Reg_F25,      24,  "f25",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F25))  \
+  X(Reg_F26,      25,  "f26",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F26))  \
+  X(Reg_F27,      26,  "f27",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F27))  \
+  X(Reg_F28,      27,  "f28",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F28))  \
+  X(Reg_F29,      28,  "f29",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F29))  \
+  X(Reg_F30,      29,  "f30",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F30))  \
+  X(Reg_F31,      30,  "f31",   1, 0, 0, 0, 0, 0, 1, 0, 0, ALIASES1(Reg_F31))
+
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
 // The following defines a table with the available pairs of consecutive i32
@@ -159,6 +191,7 @@
   /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt,         \
      isFP32, isFP64, isVec128, alias_init */                                   \
   REGMIPS32_GPR_TABLE                                                          \
+  REGMIPS32_FPR_TABLE                                                          \
   REGMIPS32_I64PAIR_TABLE
 
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
@@ -167,6 +200,8 @@
   /* val, init */                                                              \
   X(Reg_GPR_First, = Reg_ZERO)                                                 \
   X(Reg_GPR_Last,  = Reg_HI)                                                   \
+  X(Reg_FPR_First, = Reg_F0)                                                   \
+  X(Reg_FPR_Last,  = Reg_F31)                                                  \
   X(Reg_I64PAIR_First, = Reg_V0V1)                                             \
   X(Reg_I64PAIR_Last, = Reg_LOHI)                                              \
 //define X(val, init)