Adds ARM SIMD instructions.

runtime/vm/assembler_arm.cc

Index: runtime/vm/assembler_arm.cc
===================================================================
--- runtime/vm/assembler_arm.cc	(revision 25244)
+++ runtime/vm/assembler_arm.cc	(working copy)
@@ -1332,6 +1332,27 @@
 }
 
 
+void Assembler::vminqs(QRegister qd, QRegister qn, QRegister qm) {
+  EmitSIMDqqq(B21 | B11 | B10 | B9 | B8, kSWord, qd, qn, qm);
+}
+
+
+void Assembler::vmaxqs(QRegister qd, QRegister qn, QRegister qm) {
+  EmitSIMDqqq(B11 | B10 | B9 | B8, kSWord, qd, qn, qm);
+}
+
+
+void Assembler::vrecpeqs(QRegister qd, QRegister qm) {
+  EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8, kSWord,
+              qd, Q0, qm);
+}
+
+
+void Assembler::vrecpsqs(QRegister qd, QRegister qn, QRegister qm) {
+  EmitSIMDqqq(B11 | B10 | B9 | B8 | B4, kSWord, qd, qn, qm);
+}
+
+
 void Assembler::vdup(OperandSize sz, QRegister qd, DRegister dm, int idx) {
   ASSERT((sz != kDWord) && (sz != kSWord) && (sz != kWordPair));
   int code = 0;