Adds ARM SIMD instructions.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/simulator.h"
 #include "vm/runtime_entry.h"
@@ skipping 1314 matching lines @@
 void Assembler::vorrq(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B21 | B8 | B4, kByte, qd, qn, qm);
 }
 
 
 void Assembler::vornq(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B21 | B20 | B8 | B4, kByte, qd, qn, qm);
 }
 
 
+void Assembler::vminqs(QRegister qd, QRegister qn, QRegister qm) {
+  EmitSIMDqqq(B21 | B11 | B10 | B9 | B8, kSWord, qd, qn, qm);
+}
+
+
+void Assembler::vmaxqs(QRegister qd, QRegister qn, QRegister qm) {
+  EmitSIMDqqq(B11 | B10 | B9 | B8, kSWord, qd, qn, qm);
+}
+
+
+void Assembler::vrecpeqs(QRegister qd, QRegister qm) {
+  EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8, kSWord,
+              qd, Q0, qm);
+}
+
+
+void Assembler::vrecpsqs(QRegister qd, QRegister qn, QRegister qm) {
+  EmitSIMDqqq(B11 | B10 | B9 | B8 | B4, kSWord, qd, qn, qm);
+}
+
+
 void Assembler::vdup(OperandSize sz, QRegister qd, DRegister dm, int idx) {
   ASSERT((sz != kDWord) && (sz != kSWord) && (sz != kWordPair));
   int code = 0;
 
   switch (sz) {
     case kByte:
     case kUnsignedByte: {
       ASSERT((idx >= 0) && (idx < 8));
       code = 1 | (idx << 1);
       break;
@@ skipping 1128 matching lines @@
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM