Subzero: Fix srem.i8/urem.i8 lowering for x86-64.

src/IceInstX8664.def

Index: src/IceInstX8664.def
diff --git a/src/IceInstX8664.def b/src/IceInstX8664.def
index 42edba6215c3a4380b848762f2c1004883313dd5..8ed221d3a1ac3eb796bf87f39c09594f5ad7ecb1 100644
--- a/src/IceInstX8664.def
+++ b/src/IceInstX8664.def
@@ -81,13 +81,13 @@
   X(Reg_r15l, 15, "r15b", Reg_r15, 0,1,0,0,1, 1,0,0,0,1, 0, 0,0,0,1,0,         \
     REGLIST3(RegX8664, r15, r15d, r15w))                                       \
   /* High 8-bit registers.  None are allowed for register allocation. */       \
-  X(Reg_ah, 4, "ah", Reg_rax, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1,              \
+  X(Reg_ah, 4, "ah", Reg_rax, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,0,              \
     REGLIST3(RegX8664, rax, eax, ax))                                          \
-  X(Reg_ch, 5, "ch", Reg_rcx, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1,              \
+  X(Reg_ch, 5, "ch", Reg_rcx, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,0,              \
     REGLIST3(RegX8664, rcx, ecx, cx))                                          \
-  X(Reg_dh, 6, "dh", Reg_rdx, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1,              \
+  X(Reg_dh, 6, "dh", Reg_rdx, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,0,              \
     REGLIST3(RegX8664, rdx, edx, dx))                                          \
-  X(Reg_bh, 7, "bh", Reg_rbx, 0,1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1,              \
+  X(Reg_bh, 7, "bh", Reg_rbx, 0,1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,0,              \
     REGLIST3(RegX8664, rbx, ebx, bx))                                          \
   /* End of 8-bit register set */
 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,