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Issue 1909853002: Subzero: Fix srem.i8/urem.i8 lowering for x86-64. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 4 years, 8 months ago
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1 //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -*- C++ -*-===// 1 //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of lowered x86-64 instructions in the 10 // This file defines properties of lowered x86-64 instructions in the
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74 REGLIST3(RegX8664, r11, r11d, r11w)) \ 74 REGLIST3(RegX8664, r11, r11d, r11w)) \
75 X(Reg_r12l, 12, "r12b", Reg_r12, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 75 X(Reg_r12l, 12, "r12b", Reg_r12, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
76 REGLIST3(RegX8664, r12, r12d, r12w)) \ 76 REGLIST3(RegX8664, r12, r12d, r12w)) \
77 X(Reg_r13l, 13, "r13b", Reg_r13, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 77 X(Reg_r13l, 13, "r13b", Reg_r13, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
78 REGLIST3(RegX8664, r13, r13d, r13w)) \ 78 REGLIST3(RegX8664, r13, r13d, r13w)) \
79 X(Reg_r14l, 14, "r14b", Reg_r14, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 79 X(Reg_r14l, 14, "r14b", Reg_r14, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
80 REGLIST3(RegX8664, r14, r14d, r14w)) \ 80 REGLIST3(RegX8664, r14, r14d, r14w)) \
81 X(Reg_r15l, 15, "r15b", Reg_r15, 0,1,0,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \ 81 X(Reg_r15l, 15, "r15b", Reg_r15, 0,1,0,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \
82 REGLIST3(RegX8664, r15, r15d, r15w)) \ 82 REGLIST3(RegX8664, r15, r15d, r15w)) \
83 /* High 8-bit registers. None are allowed for register allocation. */ \ 83 /* High 8-bit registers. None are allowed for register allocation. */ \
84 X(Reg_ah, 4, "ah", Reg_rax, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \ 84 X(Reg_ah, 4, "ah", Reg_rax, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
85 REGLIST3(RegX8664, rax, eax, ax)) \ 85 REGLIST3(RegX8664, rax, eax, ax)) \
86 X(Reg_ch, 5, "ch", Reg_rcx, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \ 86 X(Reg_ch, 5, "ch", Reg_rcx, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
87 REGLIST3(RegX8664, rcx, ecx, cx)) \ 87 REGLIST3(RegX8664, rcx, ecx, cx)) \
88 X(Reg_dh, 6, "dh", Reg_rdx, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \ 88 X(Reg_dh, 6, "dh", Reg_rdx, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
89 REGLIST3(RegX8664, rdx, edx, dx)) \ 89 REGLIST3(RegX8664, rdx, edx, dx)) \
90 X(Reg_bh, 7, "bh", Reg_rbx, 0,1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \ 90 X(Reg_bh, 7, "bh", Reg_rbx, 0,1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
91 REGLIST3(RegX8664, rbx, ebx, bx)) \ 91 REGLIST3(RegX8664, rbx, ebx, bx)) \
92 /* End of 8-bit register set */ 92 /* End of 8-bit register set */
93 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, 93 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
94 // sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, 94 // sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8,
95 // is16To8, isTrunc8Rcvr, isAhRcvr, aliases) 95 // is16To8, isTrunc8Rcvr, isAhRcvr, aliases)
96 96
97 #define REGX8664_GPR_TABLE \ 97 #define REGX8664_GPR_TABLE \
98 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \ 98 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \
99 isGPR,is64,is32,is16,is8, isXmm, \ 99 isGPR,is64,is32,is16,is8, isXmm, \
100 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \ 100 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
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305 X(v4i1, i32, "?", "", "", "", "d", "", "") \ 305 X(v4i1, i32, "?", "", "", "", "d", "", "") \
306 X(v8i1, i16, "?", "", "", "", "w", "", "") \ 306 X(v8i1, i16, "?", "", "", "", "w", "", "") \
307 X(v16i1, i8, "?", "", "", "", "b", "", "") \ 307 X(v16i1, i8, "?", "", "", "", "b", "", "") \
308 X(v16i8, i8, "?", "", "", "", "b", "", "") \ 308 X(v16i8, i8, "?", "", "", "", "b", "", "") \
309 X(v8i16, i16, "?", "", "", "", "w", "", "") \ 309 X(v8i16, i16, "?", "", "", "", "w", "", "") \
310 X(v4i32, i32, "dq", "", "", "", "d", "", "") \ 310 X(v4i32, i32, "dq", "", "", "", "d", "", "") \
311 X(v4f32, f32, "ps", "", "ps", "ps", "d", "", "") 311 X(v4f32, f32, "ps", "", "ps", "ps", "d", "", "")
312 //#define X(tag, elementty, cvt, sdss, pdps, pack, width, fld) 312 //#define X(tag, elementty, cvt, sdss, pdps, pack, width, fld)
313 313
314 #endif // SUBZERO_SRC_ICEINSTX8664_DEF 314 #endif // SUBZERO_SRC_ICEINSTX8664_DEF
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