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Unified Diff: src/a64/macro-assembler-a64.cc

Issue 190603003: A64 tweaks for division-like operations. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 9 months ago
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Index: src/a64/macro-assembler-a64.cc
diff --git a/src/a64/macro-assembler-a64.cc b/src/a64/macro-assembler-a64.cc
index 4b1d381c29be5e14a140a9feac8e1826bba0d5df..b5a925b337b0ca8be5d89c73acb4f0f09762cf46 100644
--- a/src/a64/macro-assembler-a64.cc
+++ b/src/a64/macro-assembler-a64.cc
@@ -4936,18 +4936,15 @@ void MacroAssembler::FlooringDiv(Register result,
Register dividend,
int32_t divisor) {
Register tmp = WTmp0();
- ASSERT(!AreAliased(dividend, result, tmp));
+ ASSERT(!AreAliased(result, dividend, tmp));
+ ASSERT(result.Is32Bits() && dividend.Is32Bits());
MultiplierAndShift ms(divisor);
Mov(tmp, Operand(ms.multiplier()));
Smull(result.X(), dividend, tmp);
- Mov(result.X(), Operand(result.X(), ASR, 32));
- if (divisor > 0 && ms.multiplier() < 0) {
- Add(result, result, Operand(dividend));
- }
- if (divisor < 0 && ms.multiplier() > 0) {
- Sub(result, result, Operand(dividend));
- }
- if (ms.shift() > 0) Mov(result, Operand(result, ASR, ms.shift()));
+ Asr(result.X(), result.X(), 32);
+ if (divisor > 0 && ms.multiplier() < 0) Add(result, result, dividend);
+ if (divisor < 0 && ms.multiplier() > 0) Sub(result, result, dividend);
+ if (ms.shift() > 0) Asr(result, result, ms.shift());
Add(result, result, Operand(dividend, LSR, 31));
}
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