A64 tweaks for division-like operations.

src/a64/macro-assembler-a64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 4918 matching lines @@
   }
   return memcmp(sequence, old, kCodeAgeStubEntryOffset) == 0;
 }
 #endif
 
 
 void MacroAssembler::FlooringDiv(Register result,
                                  Register dividend,
                                  int32_t divisor) {
   Register tmp = WTmp0();
-  ASSERT(!AreAliased(dividend, result, tmp));
+  ASSERT(!AreAliased(result, dividend, tmp));
+  ASSERT(result.Is32Bits() && dividend.Is32Bits());
   MultiplierAndShift ms(divisor);
   Mov(tmp, Operand(ms.multiplier()));
   Smull(result.X(), dividend, tmp);
-  Mov(result.X(), Operand(result.X(), ASR, 32));
-  if (divisor > 0 && ms.multiplier() < 0) {
-    Add(result, result, Operand(dividend));
-  }
-  if (divisor < 0 && ms.multiplier() > 0) {
-    Sub(result, result, Operand(dividend));
-  }
-  if (ms.shift() > 0) Mov(result, Operand(result, ASR, ms.shift()));
+  Asr(result.X(), result.X(), 32);
+  if (divisor > 0 && ms.multiplier() < 0) Add(result, result, dividend);
+  if (divisor < 0 && ms.multiplier() > 0) Sub(result, result, dividend);
+  if (ms.shift() > 0) Asr(result, result, ms.shift());
   Add(result, result, Operand(dividend, LSR, 31));
 }
 
 
 #undef __
 #define __ masm->
 
 
 void InlineSmiCheckInfo::Emit(MacroAssembler* masm, const Register& reg,
                               const Label* smi_check) {
@@ skipping 36 matching lines @@
   }
 }
 
 
 #undef __
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_A64