Index: src/compiler/ppc/code-generator-ppc.cc |
diff --git a/src/compiler/ppc/code-generator-ppc.cc b/src/compiler/ppc/code-generator-ppc.cc |
index 2bf4860d4d7030cb8c7627cb8f176fe2e2400e55..8fda2569b8ef074d4b67d546a739df4a2d5b41d0 100644 |
--- a/src/compiler/ppc/code-generator-ppc.cc |
+++ b/src/compiler/ppc/code-generator-ppc.cc |
@@ -672,6 +672,20 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) { |
DCHECK_EQ(LeaveRC, i.OutputRCBit()); \ |
} while (0) |
+#define ASSEMBLE_ATOMIC_LOAD_INTEGER(asm_instr, asm_instrx) \ |
+ do { \ |
+ AddressingMode mode = kMode_None; \ |
+ DCHECK_EQ(kMode_MRR, mode); \ |
+ if (mode == kMode_MRI) { \ |
+ __ asm_instr(i.OutputRegister(), \ |
+ MemOperand(i.InputRegister(0), i.InputRegister(1))); \ |
MTBrandyberry
2016/04/19 14:13:08
If you want to support the non-indexed load form h
|
+ } else { \ |
+ __ asm_instrx(i.OutputRegister(), \ |
+ MemOperand(i.InputRegister(0), i.InputRegister(1))); \ |
+ } \ |
+ __ lwsync(); \ |
MTBrandyberry
2016/04/19 14:13:08
Joran was going to get another opinion on correctn
|
+ } while (0) |
+ |
void CodeGenerator::AssembleDeconstructFrame() { |
__ LeaveFrame(StackFrame::MANUAL); |
} |
@@ -1585,6 +1599,23 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) { |
case kCheckedStoreFloat64: |
ASSEMBLE_CHECKED_STORE_DOUBLE(); |
break; |
+ |
+ case kAtomicLoadInt8: |
+ ASSEMBLE_ATOMIC_LOAD_INTEGER(lbz, lbzx); |
+ __ extsb(i.OutputRegister(), i.OutputRegister()); |
+ break; |
+ case kAtomicLoadUint8: |
+ ASSEMBLE_ATOMIC_LOAD_INTEGER(lbz, lbzx); |
+ break; |
+ case kAtomicLoadInt16: |
+ ASSEMBLE_ATOMIC_LOAD_INTEGER(lha, lhax); |
+ break; |
+ case kAtomicLoadUint16: |
+ ASSEMBLE_ATOMIC_LOAD_INTEGER(lhz, lhzx); |
+ break; |
+ case kAtomicLoadWord32: |
+ ASSEMBLE_ATOMIC_LOAD_INTEGER(lwa, lwax); |
+ break; |
default: |
UNREACHABLE(); |
break; |