PPC: [Atomics] Remove Atomics code stubs; use TF ops

src/compiler/ppc/code-generator-ppc.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/code-generator.h"
 
 #include "src/ast/scopes.h"
 #include "src/compiler/code-generator-impl.h"
 #include "src/compiler/gap-resolver.h"
 #include "src/compiler/node-matchers.h"
@@ skipping 654 matching lines @@
     Register value = i.InputRegister(3);                      \
     if (mode == kMode_MRI) {                                  \
       __ asm_instr(value, operand);                           \
     } else {                                                  \
       __ asm_instrx(value, operand);                          \
     }                                                         \
     __ bind(&done);                                           \
     DCHECK_EQ(LeaveRC, i.OutputRCBit());                      \
   } while (0)
 
+#define ASSEMBLE_ATOMIC_LOAD_INTEGER(asm_instr, asm_instrx)           \
+  do {                                                                \
+    AddressingMode mode = kMode_None;                         \
+    DCHECK_EQ(kMode_MRR, mode);                               \
+    if (mode == kMode_MRI) {                                  \
+    __ asm_instr(i.OutputRegister(),                                  \
+                 MemOperand(i.InputRegister(0), i.InputRegister(1))); \

[MTBrandyberry, 2016/04/19 14:13:08]

If you want to support the non-indexed load form here, take a look at how other
paths contruct the MemOperand with i.MemoryOperand (see ASSEMBLE_LOAD_FLOAT for
an example).

+    } else {                                                  \
+    __ asm_instrx(i.OutputRegister(),                                  \
+                 MemOperand(i.InputRegister(0), i.InputRegister(1))); \
+    }                                                         \
+    __ lwsync();                                                      \

[MTBrandyberry, 2016/04/19 14:13:08]

Joran was going to get another opinion on correctness, but for now let's go with
the documented sequence
   [sync;  <load>; cmp; bc; isync]
implemented in the CL prior to this refactor.  See ASSEMBLE_ATOMIC_LOAD here:
https://codereview.chromium.org/1902433003/diff/20001/src/ppc/code-stubs-ppc.cc

+  } while (0)
+
 void CodeGenerator::AssembleDeconstructFrame() {
   __ LeaveFrame(StackFrame::MANUAL);
 }
 
 void CodeGenerator::AssembleSetupStackPointer() {}
 
 void CodeGenerator::AssembleDeconstructActivationRecord(int stack_param_delta) {
   int sp_slot_delta = TailCallFrameStackSlotDelta(stack_param_delta);
   if (sp_slot_delta > 0) {
     __ Add(sp, sp, sp_slot_delta * kPointerSize, r0);
@@ skipping 893 matching lines @@
 #else
       UNREACHABLE();
 #endif
       break;
     case kCheckedStoreFloat32:
       ASSEMBLE_CHECKED_STORE_FLOAT32();
       break;
     case kCheckedStoreFloat64:
       ASSEMBLE_CHECKED_STORE_DOUBLE();
       break;
+
+    case kAtomicLoadInt8:
+      ASSEMBLE_ATOMIC_LOAD_INTEGER(lbz, lbzx);
+      __ extsb(i.OutputRegister(), i.OutputRegister());
+      break;
+    case kAtomicLoadUint8:
+      ASSEMBLE_ATOMIC_LOAD_INTEGER(lbz, lbzx);
+      break;
+    case kAtomicLoadInt16:
+      ASSEMBLE_ATOMIC_LOAD_INTEGER(lha, lhax);
+      break;
+    case kAtomicLoadUint16:
+      ASSEMBLE_ATOMIC_LOAD_INTEGER(lhz, lhzx);
+      break;
+    case kAtomicLoadWord32:
+      ASSEMBLE_ATOMIC_LOAD_INTEGER(lwa, lwax);
+      break;
     default:
       UNREACHABLE();
       break;
   }
 }  // NOLINT(readability/fn_size)
 
 
 // Assembles branches after an instruction.
 void CodeGenerator::AssembleArchBranch(Instruction* instr, BranchInfo* branch) {
   PPCOperandConverter i(this, instr);
@@ skipping 447 matching lines @@
       padding_size -= v8::internal::Assembler::kInstrSize;
     }
   }
 }
 
 #undef __
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8