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Unified Diff: src/IceTargetLoweringARM32.def

Issue 1891243002: Subzero. ARM32. De-scalarizes icmp and fcmp for vectors. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Addresses comments. Created 4 years, 8 months ago
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Index: src/IceTargetLoweringARM32.def
diff --git a/src/IceTargetLoweringARM32.def b/src/IceTargetLoweringARM32.def
index 95aa2559f69a96cf0da6c0547ca46c50159c5037..c1d29f823e0bfa9b6444afb855b6917acead63ed 100644
--- a/src/IceTargetLoweringARM32.def
+++ b/src/IceTargetLoweringARM32.def
@@ -18,44 +18,52 @@
// Patterns for lowering fcmp. These are expected to be used in the following
// manner:
//
+// Scalar:
// mov reg, #0
// movCC0 reg, #1 /* only if CC0 != kNone */
// movCC1 reg, #1 /* only if CC1 != kNone */
//
-// TODO(jpp): vector lowerings.
+// Vector:
+// vcCC0_V Cmp0, Src0, Src1 /* only if CC0_V != none */
+// vcCC1_V Cmp1, Src1, Src0 /* only if CC1_V != none */
+// vorr Cmp2, Cmp0, Cmp1 /* only if CC1_V != none */
+// vmvn Reg3, Cmp? /* only if NEG_V = true */
+//
+// If INV_V = true, then Src0 and Src1 should be swapped.
+//
#define FCMPARM32_TABLE \
- /* val, CC0, CC1 */ \
- X(False, kNone, kNone) \
- X(Oeq, EQ, kNone) \
- X(Ogt, GT, kNone) \
- X(Oge, GE, kNone) \
- X(Olt, MI, kNone) \
- X(Ole, LS, kNone) \
- X(One, MI, GT) \
- X(Ord, VC, kNone) \
- X(Ueq, EQ, VS) \
- X(Ugt, HI, kNone) \
- X(Uge, PL, kNone) \
- X(Ult, LT, kNone) \
- X(Ule, LE, kNone) \
- X(Une, NE, kNone) \
- X(Uno, VS, kNone) \
- X(True, AL, kNone) \
-//#define X(val, CC0, CC1)
+ /*val , CC0 , CC1 , CC0_V, CC1_V, INV_V, NEG_V */ \
+ X(False, kNone, kNone, none , none , false, false) \
+ X(Oeq , EQ , kNone, eq , none , false, false) \
+ X(Ogt , GT , kNone, gt , none , false, false) \
+ X(Oge , GE , kNone, ge , none , false, false) \
+ X(Olt , MI , kNone, gt , none , true , false) \
+ X(Ole , LS , kNone, ge , none , true , false) \
+ X(One , MI , GT , gt , gt , false, false) \
+ X(Ord , VC , kNone, ge , gt , false, false) \
+ X(Ueq , EQ , VS , gt , gt , false, true) \
+ X(Ugt , HI , kNone, ge , none , true , true) \
+ X(Uge , PL , kNone, gt , none , true , true) \
+ X(Ult , LT , kNone, ge , none , false, true) \
+ X(Ule , LE , kNone, gt , none , false, true) \
+ X(Une , NE , kNone, eq , none , false, true) \
+ X(Uno , VS , kNone, ge , gt , false, true) \
+ X(True , AL , kNone, none , none , false, false)
+//#define X(val, CC0, CC1, CC0_V, CC1_V, INV_V, NEG_V)
// Patterns for lowering icmp.
-#define ICMPARM32_TABLE \
- /* val, is_signed, swapped64, C_32, C1_64, C2_64 */ \
- X(Eq, false, false, EQ, EQ, NE) \
- X(Ne, false, false, NE, NE, EQ) \
- X(Ugt, false, false, HI, HI, LS) \
- X(Uge, false, false, CS, CS, CC) \
- X(Ult, false, false, CC, CC, CS) \
- X(Ule, false, false, LS, LS, HI) \
- X(Sgt, true, true, GT, LT, GE) \
- X(Sge, true, false, GE, GE, LT) \
- X(Slt, true, false, LT, LT, GE) \
- X(Sle, true, true, LE, GE, LT) \
-//#define X(val, is_signed, swapped64, C_32, C1_64, C2_64)
+#define ICMPARM32_TABLE \
+ /*val, is_signed, swapped64, C_32, C1_64, C2_64, C_V, INV_V, NEG_V */ \
+ X(Eq , false , false , EQ, EQ , NE , eq , false, false) \
+ X(Ne , false , false , NE, NE , EQ , eq , false, true) \
+ X(Ugt, false , false , HI, HI , LS , gt , false, false) \
+ X(Uge, false , false , CS, CS , CC , ge , false, false) \
+ X(Ult, false , false , CC, CC , CS , gt , true , false) \
+ X(Ule, false , false , LS, LS , HI , ge , true , false) \
+ X(Sgt, true , true , GT, LT , GE , gt , false, false) \
+ X(Sge, true , false , GE, GE , LT , ge , false, false) \
+ X(Slt, true , false , LT, LT , GE , gt , true , false) \
+ X(Sle, true , true , LE, GE , LT , ge , true , false)
+//#define X(val, is_signed, swapped64, C_32, C1_64, C2_64, C_V, INV_V, NEG_V)
#endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_DEF
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