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Issue 1891243002: Subzero. ARM32. De-scalarizes icmp and fcmp for vectors. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Addresses comments. Created 4 years, 8 months ago
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1 //===- subzero/src/IceTargetLoweringARM32.def - ARM32 X-macros --*- C++ -*-===// 1 //===- subzero/src/IceTargetLoweringARM32.def - ARM32 X-macros --*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines certain patterns for lowering to ARM32 target 10 // This file defines certain patterns for lowering to ARM32 target
11 // instructions, in the form of x-macros. 11 // instructions, in the form of x-macros.
12 // 12 //
13 //===----------------------------------------------------------------------===// 13 //===----------------------------------------------------------------------===//
14 14
15 #ifndef SUBZERO_SRC_ICETARGETLOWERINGARM32_DEF 15 #ifndef SUBZERO_SRC_ICETARGETLOWERINGARM32_DEF
16 #define SUBZERO_SRC_ICETARGETLOWERINGARM32_DEF 16 #define SUBZERO_SRC_ICETARGETLOWERINGARM32_DEF
17 17
18 // Patterns for lowering fcmp. These are expected to be used in the following 18 // Patterns for lowering fcmp. These are expected to be used in the following
19 // manner: 19 // manner:
20 // 20 //
21 // Scalar:
21 // mov reg, #0 22 // mov reg, #0
22 // movCC0 reg, #1 /* only if CC0 != kNone */ 23 // movCC0 reg, #1 /* only if CC0 != kNone */
23 // movCC1 reg, #1 /* only if CC1 != kNone */ 24 // movCC1 reg, #1 /* only if CC1 != kNone */
24 // 25 //
25 // TODO(jpp): vector lowerings. 26 // Vector:
27 // vcCC0_V Cmp0, Src0, Src1 /* only if CC0_V != none */
28 // vcCC1_V Cmp1, Src1, Src0 /* only if CC1_V != none */
29 // vorr Cmp2, Cmp0, Cmp1 /* only if CC1_V != none */
30 // vmvn Reg3, Cmp? /* only if NEG_V = true */
31 //
32 // If INV_V = true, then Src0 and Src1 should be swapped.
33 //
26 #define FCMPARM32_TABLE \ 34 #define FCMPARM32_TABLE \
27 /* val, CC0, CC1 */ \ 35 /*val , CC0 , CC1 , CC0_V, CC1_V, INV_V, NEG_V */ \
28 X(False, kNone, kNone) \ 36 X(False, kNone, kNone, none , none , false, false) \
29 X(Oeq, EQ, kNone) \ 37 X(Oeq , EQ , kNone, eq , none , false, false) \
30 X(Ogt, GT, kNone) \ 38 X(Ogt , GT , kNone, gt , none , false, false) \
31 X(Oge, GE, kNone) \ 39 X(Oge , GE , kNone, ge , none , false, false) \
32 X(Olt, MI, kNone) \ 40 X(Olt , MI , kNone, gt , none , true , false) \
33 X(Ole, LS, kNone) \ 41 X(Ole , LS , kNone, ge , none , true , false) \
34 X(One, MI, GT) \ 42 X(One , MI , GT , gt , gt , false, false) \
35 X(Ord, VC, kNone) \ 43 X(Ord , VC , kNone, ge , gt , false, false) \
36 X(Ueq, EQ, VS) \ 44 X(Ueq , EQ , VS , gt , gt , false, true) \
37 X(Ugt, HI, kNone) \ 45 X(Ugt , HI , kNone, ge , none , true , true) \
38 X(Uge, PL, kNone) \ 46 X(Uge , PL , kNone, gt , none , true , true) \
39 X(Ult, LT, kNone) \ 47 X(Ult , LT , kNone, ge , none , false, true) \
40 X(Ule, LE, kNone) \ 48 X(Ule , LE , kNone, gt , none , false, true) \
41 X(Une, NE, kNone) \ 49 X(Une , NE , kNone, eq , none , false, true) \
42 X(Uno, VS, kNone) \ 50 X(Uno , VS , kNone, ge , gt , false, true) \
43 X(True, AL, kNone) \ 51 X(True , AL , kNone, none , none , false, false)
44 //#define X(val, CC0, CC1) 52 //#define X(val, CC0, CC1, CC0_V, CC1_V, INV_V, NEG_V)
45 53
46 // Patterns for lowering icmp. 54 // Patterns for lowering icmp.
47 #define ICMPARM32_TABLE \ 55 #define ICMPARM32_TABLE \
48 /* val, is_signed, swapped64, C_32, C1_64, C2_64 */ \ 56 /*val, is_signed, swapped64, C_32, C1_64, C2_64, C_V, INV_V, NEG_V */ \
49 X(Eq, false, false, EQ, EQ, NE) \ 57 X(Eq , false , false , EQ, EQ , NE , eq , false, false) \
50 X(Ne, false, false, NE, NE, EQ) \ 58 X(Ne , false , false , NE, NE , EQ , eq , false, true) \
51 X(Ugt, false, false, HI, HI, LS) \ 59 X(Ugt, false , false , HI, HI , LS , gt , false, false) \
52 X(Uge, false, false, CS, CS, CC) \ 60 X(Uge, false , false , CS, CS , CC , ge , false, false) \
53 X(Ult, false, false, CC, CC, CS) \ 61 X(Ult, false , false , CC, CC , CS , gt , true , false) \
54 X(Ule, false, false, LS, LS, HI) \ 62 X(Ule, false , false , LS, LS , HI , ge , true , false) \
55 X(Sgt, true, true, GT, LT, GE) \ 63 X(Sgt, true , true , GT, LT , GE , gt , false, false) \
56 X(Sge, true, false, GE, GE, LT) \ 64 X(Sge, true , false , GE, GE , LT , ge , false, false) \
57 X(Slt, true, false, LT, LT, GE) \ 65 X(Slt, true , false , LT, LT , GE , gt , true , false) \
58 X(Sle, true, true, LE, GE, LT) \ 66 X(Sle, true , true , LE, GE , LT , ge , true , false)
59 //#define X(val, is_signed, swapped64, C_32, C1_64, C2_64) 67 //#define X(val, is_signed, swapped64, C_32, C1_64, C2_64, C_V, INV_V, NEG_V)
60 68
61 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_DEF 69 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_DEF
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