Subzero. ARM32. Vector shifts.

tests_lit/assembler/arm32/lsr.ll

Index: tests_lit/assembler/arm32/lsr.ll
diff --git a/tests_lit/assembler/arm32/lsr.ll b/tests_lit/assembler/arm32/lsr.ll
index 45fd7f201d3621cb704735c35bd9917aa26a7df5..31be9cf08324a6c3c21faefebaa49a2c21825655 100644
--- a/tests_lit/assembler/arm32/lsr.ll
+++ b/tests_lit/assembler/arm32/lsr.ll
@@ -73,11 +73,18 @@ entry:
 
   %v = lshr <4 x i32> %a, %b
 
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; DIS:  28:        e1a00130
+; ASM:          vneg.s32  q1, q1
+; ASM-NEXT:     vshl.u32 q0, q0, q1
+; DIS:      20:          f3b923c2
+; DIS:      24:          f3220440
+; IASM:         .byte 0xc2

[Karl, 2016/04/13 16:17:37]

Same here (and below).

[John, 2016/04/15 13:20:57]

Done.

+; IASM-NEXT:    .byte 0x23
+; IASM-NEXT:    .byte 0xb9
+; IASM-NEXT:    .byte 0xf3
+; IASM-NEXT:    .byte 0x40
+; IASM-NEXT:    .byte 0x4
+; IASM-NEXT:    .byte 0x22
+; IASM-NEXT:    .byte 0xf3
 
   ret <4 x i32> %v
 }
@@ -89,14 +96,18 @@ entry:
 
   %v = lshr <8 x i16> %a, %b
 
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
+; ASM:          vneg.s16  q1, q1
+; ASM-NEXT:     vshl.u16 q0, q0, q1
+; DIS:      30:          f3b523c2
+; DIS:      34:          f3120440
+; IASM:         .byte 0xc2
+; IASM-NEXT:    .byte 0x23
+; IASM-NEXT:    .byte 0xb5
+; IASM-NEXT:    .byte 0xf3
+; IASM-NEXT:    .byte 0x40
+; IASM-NEXT:    .byte 0x4
+; IASM-NEXT:    .byte 0x12
+; IASM-NEXT:    .byte 0xf3
 
   ret <8 x i16> %v
 }
@@ -108,22 +119,18 @@ entry:
 
   %v = lshr <16 x i8> %a, %b
 
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
-; ASM:     lsr     r0, r0, r1
+; ASM:          vneg.s8  q1, q1
+; ASM-NEXT:     vshl.u8 q0, q0, q1
+; DIS:      40:         f3b123c2
+; DIS:      44:         f3020440
+; IASM:         .byte 0xc2
+; IASM-NEXT:    .byte 0x23
+; IASM-NEXT:    .byte 0xb1
+; IASM-NEXT:    .byte 0xf3
+; IASM-NEXT:    .byte 0x40
+; IASM-NEXT:    .byte 0x4
+; IASM-NEXT:    .byte 0x2
+; IASM-NEXT:    .byte 0xf3
 
   ret <16 x i8> %v
 }