Add more instructions to text-based spec.

src/trusted/validator_ragel/spec.py

Index: src/trusted/validator_ragel/spec.py
diff --git a/src/trusted/validator_ragel/spec.py b/src/trusted/validator_ragel/spec.py
index 03a062042d9b48c45c1e614ed0a02033c275ac07..6a1e5d8be954cc0ab9cc086c108575df830a3f43 100644
--- a/src/trusted/validator_ragel/spec.py
+++ b/src/trusted/validator_ragel/spec.py
@@ -217,6 +217,7 @@ REG32_TO_REG64 = {
     '%r14d' : '%r14',
     '%r15d' : '%r15'}
 
+REGS32 = REG32_TO_REG64.keys()
 REGS64 = REG32_TO_REG64.values()
 
 
@@ -424,7 +425,7 @@ def _ProcessOperandWrites(instruction, write_operands, zero_extending=False):
     if op in ['%spl', '%sp', '%rsp']:
       raise SandboxingError('changes to rsp are not allowed', instruction)
 
-    if op in REG32_TO_REG64 and zero_extending:
+    if op in REGS32 and zero_extending:
       if not postcondition.Implies(Condition()):
         raise SandboxingError(
             '%s when zero-extending %s'
@@ -510,10 +511,20 @@ def ValidateRegularInstruction(instruction, bitness):
          'xchg', 'xadd',
          'inc', 'dec', 'neg', 'not',
          'lea',
+         'adc', 'bsf', 'bsr', 'btc', 'btr', 'bts',
+         'cmp',
+         'bt',
+         'cmc',
         ]):
       return Condition(), Condition()
     elif re.match(r'mov[sz][bwl][lqw]$', name):  # MOVD, MOVSX, MOVSXD, MOVZX
       return Condition(), Condition()
+    elif name == 'bswap':
+      if ops[0] not in REGS32:
+        raise SandboxingError(
+            'bswap is only allowed with 32-bit operands',
+            instruction)
+      return Condition(), Condition()
     else:
       raise DoNotMatchError(instruction)
 
@@ -545,6 +556,33 @@ def ValidateRegularInstruction(instruction, bitness):
       write_ops = [ops[1]]
       touches_memory = False
       zero_extending = True
+    elif _InstructionNameIn(
+        name,
+        ['adc', 'bsf', 'bsr', 'btc', 'btr', 'bts']):
+      # Note: some versions of objdump (including one that is currently used
+      # in targeted tests) decode 'tzcnt' as 'repz bsf'
+      # (see validator_ragel/testdata/32/tzcnt.test)
+      # From sandboxing point of view bsf and tzcnt are the same, so
+      # we ignore this bug here.
+      # Same applies to 32-bit version.
+      assert len(ops) == 2
+      write_ops = [ops[1]]
+    elif _InstructionNameIn(name, ['cmp']):

[halyavin, 2013/07/03 10:51:14]

I think we can combine cmp and bt. They are similar enough.

[Vlad Shcherbina, 2013/07/03 11:31:21]

Done.

[Vlad Shcherbina, 2013/07/03 12:05:04]

Actually, they are not: bt %rax, (%r15) is not allowed.
Added all this logic.

+      assert len(ops) == 2
+      write_ops = []
+    elif _InstructionNameIn(name, ['bt']):
+      assert len(ops) == 2
+      write_ops = []
+    elif name == 'bswap':
+      assert len(ops) == 1
+      if ops[0] not in REGS32 + REGS64:
+        raise SandboxingError(
+            'bswap is only allowed with 32-bit and 64-bit operands',
+            instruction)
+      write_ops = ops
+    elif _InstructionNameIn(name, ['cmc']):
+      assert len(ops) == 0
+      write_ops = []
     else:
       raise DoNotMatchError(instruction)