S390: Fix Div64 sequence + DLGR simulation

S390: Fix Div64 sequence + DLGR simulation

The CodeGenerator sequence for kS390_Div64 was incorrectly defaulting
to the 32-bit divide sequence.  That case has been fixed to use the
proper 64-bit divide (DSGR).

Fix bug in DLGR simulation where the register number was being used as
operands instead of the values in those registers.

R=jyan@ca.ibm.com,michael_dawson@ca.ibm.com,mbrandy@us.ibm.com
BUG=

Committed: https://crrev.com/6aa4cc4b9448022e833dff015a74c259e473cebb
Cr-Commit-Position: refs/heads/master@{#35110}

[JoranSiu, 2016-03-29 14:14:10]

The CQ bit was checked by joransiu@ca.ibm.com to run a CQ dry run

[commit-bot: I haz the power, 2016-03-29 14:14:16]

Dry run: CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/1844563002/1
View timeline at
 https://chromium-cq-status.appspot.com/patch-timeline/1844563002/1

[JoranSiu, 2016-03-29 14:14:21]

PTAL

[john.yan, 2016-03-29 14:16:42]

lgtm

[commit-bot: I haz the power, 2016-03-29 14:51:29]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2016-03-29 14:51:29]

Dry run: This issue passed the CQ dry run.

[JoranSiu, 2016-03-29 15:04:17]

The CQ bit was checked by joransiu@ca.ibm.com

[commit-bot: I haz the power, 2016-03-29 15:04:29]

CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/1844563002/1
View timeline at
 https://chromium-cq-status.appspot.com/patch-timeline/1844563002/1

[commit-bot: I haz the power, 2016-03-29 15:06:10]

Committed patchset #1 (id:1)

[commit-bot: I haz the power, 2016-03-29 15:07:17]

Description was changed from

==========
S390: Fix Div64 sequence + DLGR simulation

The CodeGenerator sequence for kS390_Div64 was incorrectly defaulting
to the 32-bit divide sequence.  That case has been fixed to use the
proper 64-bit divide (DSGR).

Fix bug in DLGR simulation where the register number was being used as
operands instead of the values in those registers.

R=jyan@ca.ibm.com,michael_dawson@ca.ibm.com,mbrandy@us.ibm.com
BUG=
==========

to

==========
S390: Fix Div64 sequence + DLGR simulation

The CodeGenerator sequence for kS390_Div64 was incorrectly defaulting
to the 32-bit divide sequence.  That case has been fixed to use the
proper 64-bit divide (DSGR).

Fix bug in DLGR simulation where the register number was being used as
operands instead of the values in those registers.

R=jyan@ca.ibm.com,michael_dawson@ca.ibm.com,mbrandy@us.ibm.com
BUG=

Committed: https://crrev.com/6aa4cc4b9448022e833dff015a74c259e473cebb
Cr-Commit-Position: refs/heads/master@{#35110}
==========

[commit-bot: I haz the power, 2016-03-29 15:07:18]

Patchset 1 (id:??) landed as
https://crrev.com/6aa4cc4b9448022e833dff015a74c259e473cebb
Cr-Commit-Position: refs/heads/master@{#35110}