S390: Fix Div64 sequence + DLGR simulation

src/s390/simulator-s390.cc

Index: src/s390/simulator-s390.cc
diff --git a/src/s390/simulator-s390.cc b/src/s390/simulator-s390.cc
index 2aebdd8f930808e4243c5451c106e6325d5aa5af..0de702663297afa0e99870386a9db593c771ed20 100644
--- a/src/s390/simulator-s390.cc
+++ b/src/s390/simulator-s390.cc
@@ -2720,11 +2720,11 @@ bool Simulator::DecodeFourByteArithmetic(Instruction* instr) {
       RREInstruction* rreinst = reinterpret_cast<RREInstruction*>(instr);
       int r1 = rreinst->R1Value();
       int r2 = rreinst->R2Value();
-      uint64_t r1_val = static_cast<uint64_t>(r1);
-      uint64_t r2_val = static_cast<uint64_t>(r2);
+      uint64_t r1_val = get_register(r1);
+      uint64_t r2_val = get_register(r2);
       DCHECK(r1 % 2 == 0);
       unsigned __int128 dividend = static_cast<unsigned __int128>(r1_val) << 64;
-      dividend += static_cast<uint64_t>(r1 + 1);
+      dividend += get_register(r1 + 1);
       uint64_t remainder = dividend % r2_val;
       uint64_t quotient = dividend / r2_val;
       r1_val = remainder;