Prep for merging 3.4: Undo changes from 3.3 branch

lib/Target/PowerPC/PPCInstrInfo.cpp

Index: lib/Target/PowerPC/PPCInstrInfo.cpp
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 1fb17eb501595fe18e4832cc37ef45eb1054fc68..847bd224b6f2d2d2529d96f5bb40a16c2af9cdf6 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1096,11 +1096,8 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
 
   int OpC = CmpInstr->getOpcode();
   unsigned CRReg = CmpInstr->getOperand(0).getReg();
-
-  // FP record forms set CR1 based on the execption status bits, not a
-  // comparison with zero.
-  if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
-    return false;
+  bool isFP = OpC == PPC::FCMPUS || OpC == PPC::FCMPUD;
+  unsigned CRRecReg = isFP ? PPC::CR1 : PPC::CR0;
 
   // The record forms set the condition register based on a signed comparison
   // with zero (so says the ISA manual). This is not as straightforward as it
@@ -1143,9 +1140,9 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
         equalityOnly = true;
       } else
         return false;
-    } else
+    } else if (!isFP)
       equalityOnly = is64BitUnsignedCompare;
-  } else
+  } else if (!isFP)
     equalityOnly = is32BitUnsignedCompare;
 
   if (equalityOnly) {
@@ -1218,8 +1215,8 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
     unsigned IOpC = Instr.getOpcode();
 
     if (&*I != CmpInstr && (
-        Instr.modifiesRegister(PPC::CR0, TRI) ||
-        Instr.readsRegister(PPC::CR0, TRI)))
+        Instr.modifiesRegister(CRRecReg, TRI) ||
+        Instr.readsRegister(CRRecReg, TRI)))
       // This instruction modifies or uses the record condition register after
       // the one we want to change. While we could do this transformation, it
       // would likely not be profitable. This transformation removes one
@@ -1239,6 +1236,15 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
       break;
     }
 
+    if (isFP && (IOpC == PPC::FSUB || IOpC == PPC::FSUBS) &&
+        ((Instr.getOperand(1).getReg() == SrcReg &&
+          Instr.getOperand(2).getReg() == SrcReg2) ||
+        (Instr.getOperand(1).getReg() == SrcReg2 &&
+         Instr.getOperand(2).getReg() == SrcReg))) {
+      Sub = &*I;
+      break;
+    }
+
     if (I == B)
       // The 'and' is below the comparison instruction.
       return false;
@@ -1284,7 +1290,8 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
 
     // The operands to subf are the opposite of sub, so only in the fixed-point
     // case, invert the order.
-    ShouldSwap = !ShouldSwap;
+    if (!isFP)
+      ShouldSwap = !ShouldSwap;
   }
 
   if (ShouldSwap)
@@ -1323,7 +1330,7 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
   MachineBasicBlock::iterator MII = MI;
   BuildMI(*MI->getParent(), llvm::next(MII), MI->getDebugLoc(),
           get(TargetOpcode::COPY), CRReg)
-    .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
+    .addReg(CRRecReg, MIOpC != NewOpC ? RegState::Kill : 0);
 
   if (MIOpC != NewOpC) {
     // We need to be careful here: we're replacing one instruction with